Orthogonal differential vector signaling codes with embedded clock

• US 9,461,862 B2
• Filed: 08/03/2015
• Issued: 10/04/2016
• Est. Priority Date: 08/01/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Holden, Brian, Shokrollahi, Amin
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US14/816,896
• Publication Number:
  US 20160036616A1
• Time in Patent Office: 428 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 25/4919 using balanced multilevel codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 27/2637 with direct modulation of individual subcarriers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Claims

1. A method comprising:

receiving, at a plurality of multi-input comparators (MICs) via a multi-wire bus, a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal;

forming a plurality of MIC output signals, each data MIC output signal of the plurality of data MIC output signals generated by a corresponding MIC comparing a subset of symbols of the codeword, and wherein each data MIC has a set of respective data input coefficients corresponding to a respective subchannel;

generating a timing MIC output signal using a corresponding timing MIC connected to all the wires of the multi-wire bus to form a comparison of the set of symbols of the codeword, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one data signal from the timing MIC output signal; and

sampling the plurality of data MIC output signals according to the timing MIC output signal.

2. The method of claim 1, wherein at least one data MIC output signal is sampled on a rising edge of the timing MIC output signal.

3. The method of claim 1, wherein at least one data MIC output signal is sampled on a falling edge of the timing MIC output signal.

4. The method of claim 1, wherein the input vector comprises 4 sub-channels corresponding to input data signals and 1 sub-channel corresponding to a data-aligned strobe signal.

5. The method of claim 1, wherein each symbol of the set of symbols has a value selected from a set of at least two values.

6. The method of claim 5, wherein each symbol of the set of symbols has a value selected from the set of values {+1, +1/3, −

1/3, −

1}.

7. The method of claim 1, wherein the sets of respective data input coefficients and the set of timing input coefficients are determined by the non-simple orthogonal or unitary matrix.

8. The method of claim 1, wherein the codeword is balanced.

9. The method of claim 1, further comprising forming a plurality of output bits by slicing the plurality of data MIC output signals.

10. The method of claim 1, further comprising:

receiving the input vector on a plurality of wires;

generating, using an encoder, the set of symbols of the codeword representing a weighted sum of sub-channel vectors, the sub-channel vectors corresponding to rows of the non-simple orthogonal or unitary matrix, wherein a weighting of each sub-channel vector is determined by a corresponding input vector sub-channel; and

,

providing the symbols of the codeword on a multi-wire bus.

11. An apparatus comprising:

a multi-wire bus configured to receive a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal;

a plurality of data multi-input comparators (MICs) configured to form a plurality of data MIC output signals, each data MIC configured to compare a subset of symbols of the codeword, wherein each data MIC has a set of respective input coefficients corresponding to a respective subchannel;

a timing MIC connected to all the wires of the multi-wire bus, the timing MIC configured to generate a timing MIC output signal by comparing the set of symbols of the codeword, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one data signal from the timing MIC output signal; and

a plurality of sampling circuits configured to sample the plurality of data MIC output signals according to the timing MIC output signal.

12. The apparatus of claim 11, wherein at least one sampling circuit is configured to sample at least one data MIC output signal on a rising edge of the timing MIC output signal.

13. The apparatus of claim 11, wherein at least one sampling circuit is configured to sample at least one data MIC output signal on a falling edge of the timing MIC output signal.

14. The apparatus of claim 11, wherein the input vector comprises 4 sub-channels corresponding to input data signals and 1 sub-channel corresponding to a data-aligned strobe signal.

15. The apparatus of claim 11, wherein each symbol of the set of symbols has a value selected from a set of at least two values.

16. The apparatus of claim 15, wherein each symbol of the set of symbols has a value selected from the set of values {+1, +1/3, −

1/3, −

1}.

17. The apparatus of claim 11, wherein the sets of respective data input coefficients and the set of timing input coefficients are determined by the non-simple orthogonal or unitary matrix.

18. The apparatus of claim 11, wherein the codeword is balanced.

19. The apparatus of claim 11, further comprising a plurality of slicers configured to generate a set of output bits by slicing the set of data MIC output signals.