Orthogonal differential vector signaling codes with embedded clock
First Claim
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1. A method comprising:
- receiving, at a plurality of multi-input comparators (MICs) via a multi-wire bus, a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal;
forming a plurality of MIC output signals, each data MIC output signal of the plurality of data MIC output signals generated by a corresponding MIC comparing a subset of symbols of the codeword, and wherein each data MIC has a set of respective data input coefficients corresponding to a respective subchannel;
generating a timing MIC output signal using a corresponding timing MIC connected to all the wires of the multi-wire bus to form a comparison of the set of symbols of the codeword, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one data signal from the timing MIC output signal; and
sampling the plurality of data MIC output signals according to the timing MIC output signal.
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Abstract
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
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Citations
19 Claims
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1. A method comprising:
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receiving, at a plurality of multi-input comparators (MICs) via a multi-wire bus, a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal; forming a plurality of MIC output signals, each data MIC output signal of the plurality of data MIC output signals generated by a corresponding MIC comparing a subset of symbols of the codeword, and wherein each data MIC has a set of respective data input coefficients corresponding to a respective subchannel; generating a timing MIC output signal using a corresponding timing MIC connected to all the wires of the multi-wire bus to form a comparison of the set of symbols of the codeword, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one data signal from the timing MIC output signal; and sampling the plurality of data MIC output signals according to the timing MIC output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a multi-wire bus configured to receive a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal; a plurality of data multi-input comparators (MICs) configured to form a plurality of data MIC output signals, each data MIC configured to compare a subset of symbols of the codeword, wherein each data MIC has a set of respective input coefficients corresponding to a respective subchannel; a timing MIC connected to all the wires of the multi-wire bus, the timing MIC configured to generate a timing MIC output signal by comparing the set of symbols of the codeword, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one data signal from the timing MIC output signal; and a plurality of sampling circuits configured to sample the plurality of data MIC output signals according to the timing MIC output signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification