System and method for high speed packet transmission
First Claim
1. A method for data transmission comprising:
- implementing dual bi-directional data pipelines through a first processor coupled to first and second memory structures and a backplane, the first processor comprising a first transmit core and a second transmit core, wherein implementing the dual bi-directional data pipelines comprises;
receiving, at the first transmit core, a first packet from the first memory structure;
receiving, at the first transmit core, a second packet from the backplane or the second transmit core;
processing, by the first transmit core, the received first packet and the received second packet;
causing, by the first transmit core, the processed second packet to be stored in the first memory structure;
receiving, at the second transmit core, a third packet from the second memory structure;
receiving, at the second transmit core, a fourth packet from the backplane or the first transmit core;
processing, by the second transmit core, the received third packet and the received fourth packet; and
causing, by the second transmit core, the processed fourth packet to be stored in the second memory structure,wherein the processing by the first transmit core and the processing by the second transmit core are performed in parallel.
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Accused Products
Abstract
The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.
571 Citations
14 Claims
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1. A method for data transmission comprising:
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implementing dual bi-directional data pipelines through a first processor coupled to first and second memory structures and a backplane, the first processor comprising a first transmit core and a second transmit core, wherein implementing the dual bi-directional data pipelines comprises; receiving, at the first transmit core, a first packet from the first memory structure; receiving, at the first transmit core, a second packet from the backplane or the second transmit core; processing, by the first transmit core, the received first packet and the received second packet; causing, by the first transmit core, the processed second packet to be stored in the first memory structure; receiving, at the second transmit core, a third packet from the second memory structure; receiving, at the second transmit core, a fourth packet from the backplane or the first transmit core; processing, by the second transmit core, the received third packet and the received fourth packet; and causing, by the second transmit core, the processed fourth packet to be stored in the second memory structure, wherein the processing by the first transmit core and the processing by the second transmit core are performed in parallel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system comprising:
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first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces; first and second integrated circuits (IC) coupled to the MAC interfaces and at least one memory structure, the first and second ICs each configured to perform initial processing of packets received from the associated first and second MAC interfaces, respectively, and to schedule the transmission of packets to the first and second MAC interfaces, respectively, the first and second ICs each further operative to dispatch and retrieve packets to and from at least one memory structure; and a third IC coupled between the at least one memory structure and a backplane, the third IC operative to retrieve and dispatch packets to and from the at least one memory structure and the backplane, compute appropriate destinations for packets and organize packets for transmission. - View Dependent Claims (12, 13, 14)
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Specification