128 Gigabit fibre channel physical architecture

• US 9,461,941 B2
• Filed: 06/18/2014
• Issued: 10/04/2016
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Mehta, Anil, Kipp, Scott
• Primary Examiner(s): Pham, Chi H
• Assistant Examiner(s): Kumar, Shailendra
• Application Number:
  US14/308,143
• Publication Number:
  US 20140376566A1
• Time in Patent Office: 839 Days
• US Class Current: 1/1
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04L 12/4013 Management of data rate on the bus systems modifying transmission characteristics according to link quality H04L1/0001
• CPC Class Codes: H04L 41/0681 Configuration of triggering conditions
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 69/321 Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers

Abstract

The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.

Claims

1. A physical layer network interface link apparatus comprising:

a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip,

wherein said combined PCS and RS FEC module includes;

a media access control (MAC) interface for connection to a MAC layer providing or receiving a stream of 64 bit blocks;

a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes;

an RS FEC encoder module; and

an RS FEC decoder module, and

wherein said combined PCS and RS FEC module operates using only four lanes.

2. The apparatus of claim 1, said combined PCS and RS FEC module further including:

a transmit path; and

a receive path,

wherein said transmit path includes;

an encode module connected to said MAC interface;

a scramble module connected to said encode module;

a block distribution module connected to said scramble module;

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks connected to said block distribution module;

an alignment marker insertion module connected to said transmit transcode module;

said RS FEC encode module connected to said alignment marker insertion module; and

a symbol distribution module connected to said RS FEC encode module and said PMA interface, and

wherein said receive path further includes;

an alignment lock and deskew module connected to said PMA interface;

a lane reorder module connected to said alignment lock and deskew module;

said RS FEC decoder module connected to said lane reorder module;

an alignment marker removal module connected to said RS FEC decoder module;

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

a descramble module connected to said receive transcode module;

a decode module connected to said descramble module and said MAC interface.

3. The apparatus of claim 2, wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

4. The apparatus of claim 3, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

5. The apparatus of claim 2, where there is only a single alignment marker insertion module and a single alignment marker removal module in said combined PCS and RS FEC module.

6. The apparatus of claim 1, wherein the network interface link is a 128 Gbps Fibre Channel network link.

7. A physical layer network interface link apparatus comprising:

a media access control (MAC) layer having an interface providing or receiving a stream of 64 bit blocks; and

a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip,

wherein said combined PCS and RS FEC module includes;

a MAC interface connected to said MAC layer interface;

a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes;

an RS FEC encoder module; and

an RS FEC decoder module, and

wherein said combined PCS and RS FEC module operates using only four lanes.

8. The apparatus of claim 7, said combined PCS and RS FEC module further including:

a transmit path; and

a receive path,

wherein said transmit path includes;

an encode module connected to said MAC interface;

a scramble module connected to said encode module;

a block distribution module connected to said scramble module;

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks connected to said block distribution module;

an alignment marker insertion module connected to said transmit transcode module;

said RS FEC encode module connected to said alignment marker insertion module; and

a symbol distribution module connected to said RS FEC encode module and said PMA interface, and

wherein said receive path further includes;

an alignment lock and deskew module connected to said PMA interface;

a lane reorder module connected to said alignment lock and deskew module;

said RS FEC decoder module connected to said lane reorder module;

an alignment marker removal module connected to said RS FEC decoder module;

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

a descramble module connected to said receive transcode module;

a decode module connected to said descramble module and said MAC interface.

9. The apparatus of claim 8, wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

10. The apparatus of claim 9, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

11. The apparatus of claim 8, where there is only a single alignment marker insertion module and a single alignment marker removal module in said combined PCS and RS FEC module.

12. The apparatus of claim , wherein the network interface link is a 128 Gbps Fibre Channel network link.

13. A network switch comprising:

a control processor;

memory coupled to said control processor; and

a switching system coupled to said control processor, said switching system including;

a frame data storage system;

a header processing system coupled to said frame data storage system; and

a plurality of ports coupled to said frame data storage system, each of said plurality of ports including;

a frame data storage system interface coupled to said frame data storage system; and

a physical layer network interface link apparatus including;

a media access control (MAC) layer having an interface providing or receiving a stream of 64 bit blocks;

a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip;

a physical media attachment (PMA) layer having an interface connected to said combined PCS and RS FEC module; and

a physical media dependent (PMD) layer connected to said PMA layer and for connection to an external network link,

wherein said combined PCS and RS FEC module includes;

a MAC interface connected to said MAC layer interface;

a PMA interface connected to said PMA layer interface utilizing four lanes;

an RS FEC encoder module; and

an RS FEC decoder module, and

wherein said combined PCS and RS FEC module operates using only four lanes.

14. The network switch of claim 13, said combined PCS and RS FEC module further including:

a transmit path; and

a receive path,

wherein said transmit path includes;

an encode module connected to said MAC interface;

a scramble module connected to said encode module;

a block distribution module connected to said scramble module;

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks connected to said block distribution module;

an alignment marker insertion module connected to said transmit transcode module;

said RS FEC encode module connected to said alignment marker insertion module; and

a symbol distribution module connected to said RS FEC encode module and said PMA interface, and

wherein said receive path further includes;

an alignment lock and deskew module connected to said PMA interface;

a lane reorder module connected to said alignment lock and deskew module;

said RS FEC decoder module connected to said lane reorder module;

an alignment marker removal module connected to said RS FEC decoder module;

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

a descramble module connected to said receive transcode module;

a decode module connected to said descramble module and said MAC interface.

15. The network switch of claim 14, wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

16. The network switch of claim 15, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

17. The network switch of claim 14, where there is only a single alignment marker insertion module and a single alignment marker removal module in said combined PCS and RS FEC module.

18. The network switch of claim 13, wherein the external network interface link is a 128 Gbps Fibre Channel network link.