Circuits for and methods of providing a charge device model ground path using substrate taps in an integrated circuit device

• US 9,462,674 B1
• Filed: 08/26/2013
• Issued: 10/04/2016
• Est. Priority Date: 08/26/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lo, Kuok-Khian, Fakhruddin, Mohammed, Karp, James
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/010,059
• Time in Patent Office: 1,135 Days
• Field of Search: 716116-117, 716118-119, 716121-122, 326 37- 38, 326/41, 326 47- 50
• US Class Current: 1/1
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection

Abstract

A circuit for providing a ground path in an integrated circuit device is described. The circuit comprises a device region formed in a substrate; a substrate tap formed adjacent to the device region; and a conductive path coupled between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias, wherein the conductive path is configured to meet a predetermined design requirement.

Claims

1. A circuit for providing a ground path in an integrated circuit device, the circuit comprising:

a device region formed in the substrate;

a substrate tap formed adjacent to the device region; and

a conductive path coupled between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias, the conductive path comprising traces in metal layers associated with a CAD layer providing an electrostatic discharge protection circuit,

wherein the association of the traces in metal layers with the CAD layer providing an electrostatic discharge protection circuit enables the conductive path to be re-routed to meet a resistance value that is below a predetermined resistance value.

2. The circuit of claim 1, wherein the resistance value of the conductive path is a resistance value associated with metal layers between the substrate and the ground metal layer of the integrated circuit device.

3. The circuit of claim 2, wherein a re-routed conductive path is provided between the substrate tap and the ground metal layer if the resistance value of the conductive path is not below the predetermined resistance value.

4. The circuit of claim 1, wherein the conductive path between the substrate tap and a ground metal layer comprises a conductive path between the substrate tap and a VSS ground plane.

5. The circuit of claim 1, wherein the conductive path comprises a CDM path.

6. A method of providing a ground path in an integrated circuit device, the method comprising:

forming a device region in a substrate of the integrated circuit device;

forming a substrate tap adjacent to the device region in the integrated circuit device;

associating traces in metal layers of a conductive path with a CAD layer providing an electrostatic discharge protection circuit;

providing the conductive path between the substrate tap and a ground metal layer by way of the traces in metal layers and vias of the integrated circuit device, and

re-routing the conductive path between the substrate tap and the ground metal layer if a resistance value of the conductive path is not below a minimum resistance value, wherein the re-routed conductive path has a resistance value that is below the minimum resistance value.

7. The method of claim 6, further comprising extracting the resistance value associated with the conductive path.

8. The method of claim 7, wherein extracting the resistance value comprises determining a resistance value associated with the traces in metal layers between the substrate and the ground metal layer.

9. The method of claim 6, wherein providing the conductive path between the substrate tap and a ground metal layer comprises providing the conductive path between the substrate tap and a VSS ground plane.

10. The method of claim 6, wherein providing the conductive path between the substrate tap and a ground metal layer comprises providing a CDM path.

11. A method of providing a ground path in an integrated circuit device, the method comprising:

receiving a circuit design having a substrate tap adjacent to a device region formed in a substrate of the integrated circuit device and a conductive path extending between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias of the integrated circuit device;

associating traces in the metal layers of the conductive path with a CAD layer providing an electrostatic discharge protection circuit;

extracting a resistance value associated with the conductive path;

determining whether the resistance value associated with the conductive path is below a predetermined resistance value; and

reconfiguring the circuit design if the resistance value associated with conductive path is not below the predetermined resistance value.

12. The method of claim 11, wherein determining whether the resistance value associated with the conductive path is below a predetermined resistance value comprises determining the resistance value associated with predetermined metal layers of the conductive path.

13. The method of claim 12, wherein determining the resistance value associated with predetermined metal layers of the conductive path comprises determining the resistance value associated with metal layers below a ground plane.

14. The method of claim 11, wherein receiving a circuit design having a conductive path between the substrate tap and a ground metal layer comprises receiving a circuit design having a conductive path between the substrate tap and a VSS ground plane.

15. The method of claim 14, wherein determining whether the extracted resistance value is below a predetermined resistance value comprises determining whether a resistance between the substrate tap and the VSS ground plane is below a predetermined resistance value.

16. The method of claim 11, wherein receiving a circuit design having a conductive path between the substrate tap and a ground metal layer comprises receiving a circuit design having a CDM path.

17. The method of claim 16, wherein the CDM path comprises a plurality of CDM metal layers that overlap.