Substrate for in-cell type touch sensor liquid crystal display device and method of fabricating the same

• US 9,465,246 B2
• Filed: 11/03/2015
• Issued: 10/11/2016
• Est. Priority Date: 04/21/2011
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Min-Su, Lee, Myeong-Sik
• Primary Examiner(s): Briggs, Nathanael R
• Assistant Examiner(s): GROSS, ALEXANDER P
• Application Number:
  US14/930,902
• Publication Number:
  US 20160054609A1
• Time in Patent Office: 343 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/047 using sets of wires, e.g. crossed wires
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor

Abstract

An array substrate for an in-cell type touch sensor liquid crystal display device includes: a substrate; a gate line and a data line on the substrate; a thin film transistor connected to the gate line and the data line; a first passivation layer on the thin film transistor; a common electrode on the first passivation layer; an etching preventing pattern covering the drain contact hole; an x sensing line and a y sensing line on the common electrode; a second passivation layer on the x sensing line and the y sensing line; and a pixel electrode on the second passivation layer.

Claims

1. A method of fabricating an array substrate for an in-cell type touch sensor liquid crystal display device, the method comprising:

forming a gate line, an auxiliary sensing line, a data line, and a thin film transistor on a substrate including a plurality of touch blocks each including a plurality of pixel regions, the gate line and the data line crossing each other with an interlayer insulating layer interposed therebetween to define each of the plurality of pixel regions, the auxiliary sensing line formed under the interlayer insulating layer, and the thin film transistor connected to the gate line and the data line;

forming a first passivation layer on the thin film transistor, the first passivation layer having a first drain contact hole exposing a drain electrode of the thin film transistor;

forming a common electrode and an etching preventing pattern on the first passivation layer, the common electrode disposed in each of the plurality of touch blocks, the etching preventing pattern spaced apart from the common electrode, and the etching preventing pattern having an area greater than the drain contact hole to completely cover the drain electrode;

forming an x sensing line and a y sensing line on the common electrode, the x sensing line overlapping the gate line and the y sensing line overlapping the data line;

forming a second passivation layer on the x sensing line and the y sensing line, the second passivation layer having a second drain contact hole exposing the etching preventing pattern; and

forming a pixel electrode and a connecting pattern on the second passivation layer in each of the plurality of pixel regions, the pixel electrode contacting the etching preventing pattern through the second drain contact hole and having a plurality of open areas each having a bar shape,

wherein the first passivation layer has a first sensing hole exposing the interlayer insulating layer corresponding to an end portion of the x sensing line,

wherein the second passivation layer has a second sensing hole exposing the end portion of the x sensing line in the first contact hole,

wherein the interlayer insulating layer has a third sensing hole exposing an end portion of the auxiliary sensing line, and

wherein the connecting pattern contacts the end portion of the x sensing line and the end portion of the auxiliary sensing line.

2. The method according to claim 1, wherein:

adjacent two of the plurality of touch blocks along a first direction parallel to the gate line are connected to each other through the x sensing line;

each of the plurality of touch blocks includes first, second, and third areas;

the second areas of adjacent two of the plurality of touch blocks along a second direction parallel to the data line are connected to the y sensing line; and

the common electrode include three plate patterns separated in the first, second and third areas.

3. The method according to claim 2, wherein:

the x sensing line of the first area is separated from the x sensing line of the second area; and

the x sensing line of the second area is separated from the x sensing line of the third area.

4. The method according to claim 3, wherein:

the auxiliary sensing line is formed in the second area of each of the plurality of touch blocks to be parallel to the gate line;

the auxiliary sensing line has a same layer and a same material as the gate line; and

the x sensing line of the first area and the x sensing line of the third area are connected to each other through the auxiliary sensing line.

5. The method according to claim 1, wherein:

the common electrode has a first open area corresponding to the thin film transistor and a second open area corresponding to the first sensing hole; and

an area of the second open area is greater than an area of the first open area.

6. The method according to claim 5, wherein:

the plurality of touch blocks arranged along the first direction are electrically connected to each other through the x sensing line; and

the plurality of touch blocks arranged along the second direction are electrically connected to each other through the y sensing line.

7. The method according to claim 1, further comprising:

forming a gate link line and a gate pad connected to the gate link line together with the gate line;

forming a data link line and a data pad connected to the data link line together with the data line; and

forming a first auxiliary pad pattern together with the common electrode,

wherein the substrate includes an active area displaying an image and a non-active area surrounding the active area,

wherein the non-active area display area includes a pad area,

wherein the gate link line and the data link line are disposed in the non-active area,

wherein the gate pad and the data pad are disposed in the pad area,

wherein the gate pad and the data pad are exposed outside the first passivation, and

wherein the first auxiliary pad pattern completely covers the gate pad and the data pad.

8. The method according to claim 7, further comprising:

forming a gate pad terminal and a data pad terminal together with the pixel electrode,

wherein the second passivation layer has a data pad contact hole exposing the first auxiliary pad pattern,

wherein the second passivation layer and the interlayer insulating layer have a gate pad contact hole exposing the gate pad,

wherein the gate pad terminal contacts the gate pad through the gate pad contact hole, and

wherein the data pad terminal contacts the first auxiliary pad pattern through the data pad contact hole.

9. The method according to claim 1, wherein forming the thin film transistor comprises:

forming an intrinsic amorphous silicon layer on the substrate;

crystallizing the intrinsic amorphous silicon layer into a polycrystalline silicon layer;

patterning the polycrystalline silicon layer to form a semiconductor layer of polycrystalline silicon;

forming a gate insulating layer on the semiconductor layer;

forming a gate electrode on the gate insulating layer over the semiconductor layer, the gate electrode being connected to the gate line;

doping the semiconductor layer with impurities using the gate electrode as a doping mask to define a first semiconductor region of intrinsic polycrystalline silicon and a second semiconductor region of impurity-doped polycrystalline silicon at both sides of the first semiconductor region;

forming the interlayer insulating layer on the gate electrode, the interlayer insulating layer having a semiconductor contact hole exposing the second semiconductor region; and

forming a source electrode and the drain electrode on the interlayer insulating layer, the source and drain electrodes contacting the second semiconductor region through the semiconductor contact hole.