Multi-core synchronization mechanism

• US 9,465,432 B2
• Filed: 05/19/2014
• Issued: 10/11/2016
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry
• Primary Examiner(s): Connolly, Mark
• Assistant Examiner(s): STEWART, KEVIN MICHAEL
• Application Number:
  US14/281,434
• Publication Number:
  US 20150067369A1
• Time in Patent Office: 876 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 9/522 Barrier synchronisation

Abstract

A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

Claims

1. A microprocessor, comprising:

a control unit, configured to selectively control a respective clock signal to each of a plurality of processing cores;

the plurality of processing cores, each configured to separately write a value to the control unit;

wherein, for each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit;

wherein the control unit is configured to detect a condition has occurred by determining that all of the plurality of processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the plurality of processing cores; and

wherein the control unit is configured to simultaneously turn on the respective clock signal to all of the plurality of processing cores in response to detecting the condition has occurred.

2. The microprocessor of claim 1, wherein:

wherein the control unit is configured to detect the condition has occurred by determining that all of the plurality of processing cores have written the same value to the control unit and the control unit has turned off the respective clock signal to all of the cores.

3. The microprocessor of claim 2, wherein if the control unit detects one of the plurality of processing cores writes a value different from the value previously written by other of the plurality of processing cores, the control unit is configured to indicate a deadlock condition and to turn on the respective clock signal to all of the plurality of processing cores for which it previously turned off the respective clock signal.

4. The microprocessor of claim 1, wherein the value written by each of the plurality of processing cores includes an indicator that indicates whether or not the value includes a sleep state, wherein the control unit is configured to detect the condition has occurred by determining that all of the plurality of processing cores have written a value to the control unit in which the indicator indicates the value includes a sleep state.

5. The microprocessor of claim 4, wherein an operating system running on the core executes a sleep instruction to specify the sleep state to the core.

6. The microprocessor of claim 4, further comprising:

a status register, readable by each of the plurality of processing cores, wherein when the control unit detects the condition has occurred the control unit populates the status register with a lowest common value of the sleep state written by each of the plurality of processing cores.

7. The microprocessor of claim 1, wherein the value written by each of the plurality of processing cores includes a selective wakeup indicator, wherein in response to detecting the condition has occurred the control unit is configured to turn on the respective clock signal to only a temporally last of the plurality of processing cores to write the value.

8. The microprocessor of claim 1, further comprising:

for each core of the plurality of processing cores, an indicator that indicates whether the core is enabled or disabled; and

wherein the control unit is configured to detect the condition has occurred by determining that all of the enabled cores of the plurality of processing cores have written a value to the control unit without regard for whether the disabled cores have written a value to the control unit.

9. The microprocessor of claim 1, further comprising:

wherein the control unit is configured to determine that the value written by each of the plurality of processing cores specifies a subset of the plurality of processing cores that is less than all of the plurality of processing cores; and

wherein the control unit is configured to detect the condition has occurred by determining that all of the plurality of processing cores included in the subset have written a value to the control unit without regard for whether the plurality of processing cores excluded from the subset have written a value to the control unit.

10. The microprocessor of claim 9, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores located on a same semiconductor die as the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores located on a different semiconductor die as the one of the plurality of processing cores that wrote the value are excluded from the subset.

11. The microprocessor of claim 9, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores located on a different semiconductor die as the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores located on a same semiconductor die as the one of the plurality of processing cores that wrote the value are excluded from the subset.

12. The microprocessor of claim 9, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores that share a cache memory with the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores that do not share a cache memory with the one of the plurality of processing cores that wrote the value are excluded from the subset.

13. The microprocessor of claim 1, wherein the value written by each of the plurality of processing cores includes a field that specifies one or more wakeup events, wherein the control unit is configured to turn on the respective clock signal to the core when the control unit detects one or more of the specified one or more wakeup events has occurred.

14. The microprocessor of claim 1, wherein to simultaneously turn on the respective clock signal to all of the plurality of processing cores the control unit is configured to turn on the respective clock signal to all of the plurality of processing cores on the same clock cycle.

31. The microprocessor of claim 1, further comprising a processor die, wherein the control unit and the plurality of cores are in the processor die.

32. The microprocessor of claim 31, further comprising an uncore address/data bus on the die that provides micro-architectural address space to resources of the die that are shared by the plurality of cores, wherein each core is configured to write a value to the control unit over the uncore address/data bus.

33. The microprocessor of claim 31, further comprising:

a plurality of control unit registers, wherein a separate register is provided for each core;

wherein each core is configured to separately write a value to the corresponding control unit register; and

wherein the control unit is configured to detect that a condition has occurred by determining that a common value has been written by each of the plurality of processing cores, or by each of the cores of a defined subset of the processing cores, to each of the corresponding control unit registers, and the control unit has turned off the respective clock signal to all of the plurality of processing cores.

15. In a microprocessor having a control unit and a plurality of processing cores, a method for synchronizing operations among the cores, the method comprising:

writing, by each of the plurality of processing cores, a value to the control unit;

turning off, by the control unit for each core of the plurality of processing cores, a respective clock signal to the core in response to the core said writing a value to the control unit;

detecting, by the control unit, that a condition has occurred by determining that all of the plurality of processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the plurality of processing cores; and

turning on, by the control unit, simultaneously the respective clock signal to all of the plurality of processing cores in response to said detecting the condition has occurred.

16. The method of claim 15, wherein:

wherein said detecting the condition has occurred by determining that all of the plurality of processing cores have written the same value to the control unit and the control unit has turned off the respective clock signal to all of the cores.

17. The method of claim 16, further comprising:

detecting, by the control unit, that one of the plurality of processing cores writes a value different from the value previously written by other of the plurality of processing cores; and

indicating, by the control unit, a deadlock condition and turning on the respective clock signal to all of the plurality of processing cores for which it previously turned off the respective clock signal.

18. The method of claim 15, wherein the value written by each of the plurality of processing cores includes an indicator that indicates whether or not the value includes a sleep state, wherein said detecting the condition has occurred by determining that all of the plurality of processing cores have written a value to the control unit in which the indicator indicates the value includes a sleep state.

19. The method of claim 18, wherein an operating system running on the core executes a sleep instruction to specify the sleep state to the core.

20. The method of claim 18, the method further comprising:

detecting, by the control unit, the condition has occurred; and

populating, by the control unit, a status register, readable by each of the plurality of processing cores, with a lowest common value of the sleep state written by each of the plurality of processing cores.

21. The method of claim 15, wherein the value written by each of the plurality of processing cores includes a selective wakeup indicator, the method further comprising:

in response to detecting the condition has occurred, turning on, by the control unit, the respective clock signal to only a temporally last of the plurality of processing cores to write the value.

22. The method of claim 15, wherein the microprocessor also includes for each core of the plurality of processing cores, an indicator that indicates whether the core is enabled or disabled, wherein said detecting the condition has occurred by determining that all of the enabled cores of the plurality of processing cores have written a value to the control unit without regard for whether the disabled cores have written a value to the control unit.

23. The method of claim 15, further comprising:

determining, by the control unit, that the value written by each of the plurality of processing cores specifies a subset of the plurality of processing cores that is less than all of the plurality of processing cores; and

wherein said detecting the condition has occurred by determining that all of the plurality of processing cores included in the subset have written a value to the control unit without regard for whether the plurality of processing cores excluded from the subset have written a value to the control unit.

24. The method of claim 23, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores located on a same semiconductor die as the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores located on a different semiconductor die as the one of the plurality of processing cores that wrote the value are excluded from the subset.

25. The method of claim 23, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores located on a different semiconductor die as the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores located on a same semiconductor die as the one of the plurality of processing cores that wrote the value are excluded from the subset.

26. The method of claim 23, wherein the value written by each of the plurality of processing cores specifies that ones of the plurality of processing cores that share a cache memory with the one of the plurality of processing cores that wrote the value are included in the subset and ones of the plurality of processing cores that do not share a cache memory with the one of the plurality of processing cores that wrote the value are excluded from the subset.

27. The method of claim 15, wherein the value written by each of the plurality of processing cores includes a field that specifies one or more wakeup events, wherein the control unit is configured to turn on the respective clock signal to the core when the control unit detects one or more of the specified one or more wakeup events has occurred.

28. The method of claim 15, wherein said turning on simultaneously the respective clock signal to all of the plurality of processing cores comprises turning on the respective clock signal to all of the plurality of processing cores on the same clock cycle.

29. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

first program code for specifying a control unit, configured to selectively control a respective clock signal to each of a plurality of processing cores; and

second program code for specifying the plurality of processing cores, each configured to separately write a value to the control unit;

wherein, for each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit;

wherein the control unit is configured to detect a condition has occurred by determining that all of the plurality of processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the plurality of processing cores; and

wherein the control unit is configured to simultaneously turn on the respective clock signal to all of the plurality of processing cores in response to detecting the condition has occurred.

30. The computer program product of claim 29, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.