Method for monitoring the coordinated execution of sequenced tasks by an electronic card comprising at least two processors synchronized to one and the same clock

• US 9,465,672 B2
• Filed: 07/24/2013
• Issued: 10/11/2016
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: Airbus Operations SAS (Airbus SE)
• Original Assignee: Airbus Operations SAS (Airbus SE)
• Inventors: Tost, Gilles, Roblero Martinez, David, Dejean, Thierry, Deneuville, Sophie, Marliere, Laurent, Blouin, Hlne
• Primary Examiner(s): Truong, Camquy
• Application Number:
  US13/949,826
• Publication Number:
  US 20140033224A1
• Time in Patent Office: 1,175 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0715 in a system implementing multitasking multitasking per se G06F9/46
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method for monitoring the coordinated execution of sequenced tasks by an electronic card including at least one first processor (PP1) and a second processor (PP2) synchronized to the same clock of determined time period, includes:

• • recording in memory means by the first processor (PP1) of a first identifier (ID1) characterizing the time period (T1) in the course of which the first sequenced task has been executed;
  • recording in the memory means by the second processor (PP2) of a second identifier (ID2) characterizing the time period (T1) in the course of which the first accessory task (N1) has been executed;
  • comparing by the first processor (PP1) the first identifier (ID1) and the second identifier (ID2); and
  • signaling by the first processor (PP1) in the case of failure of the comparison so as to signal a defect of coordination of the processors (PP1, PP2).

Claims

1. A method for monitoring the coordinated execution of sequenced tasks by an electronic card comprising at least first processor and second processor synchronized to one and the same clock of determined time period, the execution of the sequenced tasks being distributed between the processors, in which method:

over a determined time period, the first processor executes a first sequenced task while the second processor executes a first accessory task;

over the consecutive time period, the second processor executes a second sequenced task subsequent to the first sequenced task;

said method comprising

a step of recording in memory means by the first processor of a first identifier characterizing the time period in the course of which the first sequenced task has been executed, the recording step being carried out in the course of the determined time period after execution of the first sequenced task;

a step of recording in the memory means by the second processor of a second identifier characterizing the time period in the course of which the first accessory task has been executed, the recording step being carried out in the course of the determined time period after execution of the first accessory task;

a step of comparison by the first processor of the first identifier and of the second identifier recorded in the memory means, the comparison step being carried out in the course of the consecutive time period; and

a step of signaling by the first processor in the case of failure of the comparison so as to signal a defect of coordination of the processors.

2. The monitoring method as claimed in claim 1, further comprising, the first processor executing a second accessory task over the consecutive time period, wherein the comparison step is carried out in the course of the consecutive time period before the execution of the second accessory task.

3. The monitoring method as claimed in claim 1, wherein the method further comprises:

a step of comparison by the second processor of the first identifier and of the second identifier recorded in the memory means, the comparison step being carried out in the course of the consecutive time period before the execution of the second sequenced task; and

a step of signaling by the second processor in the case of failure of the comparison so as to signal a defect of coordination of the first and second processors.

4. The monitoring method as claimed in claim 1, wherein the recording steps are implemented directly after the execution of the first accessory task and of the first sequenced task.

5. The monitoring method as claimed in claim 1, wherein the steps of the monitoring method are implemented at each time period.

6. The monitoring method as claimed in claim 1, wherein the memory means comprises a RAM memory linked to the first and second processors.

7. The monitoring method as claimed in claim 1, wherein the memory means are independent of the first and second processors.

8. The monitoring method as claimed in claim 1, wherein the memory means belong to at least one of the first and second processors.

10. The monitoring method as claimed in claim 1, wherein the electronic device comprises at least first and second auxiliary electronic cards, and

wherein each of the first and second main processor of the main electronic card monitors the coordination of the execution of the sequenced tasks by each of the first and second auxiliary processors.

9. A method for monitoring the coordinated execution of sequenced tasks by an electronic card, wherein, the electronic card being a main electronic card of an electronic device comprising at least first and second main processors synchronized to a main clock of determined main time period, the electronic device furthermore comprising at least one auxiliary electronic card comprising at least one auxiliary processor synchronized to an auxiliary clock of determined auxiliary time period, the auxiliary clock being faster than the main clock, sequenced tasks having to be carried out simultaneously by one of the first and second main processors and the auxiliary processor, in which method:

over a determined main time period, the one of the first and second main processors executes a first sequenced task while the auxiliary processor executes instructions of the first sequenced task over a plurality of auxiliary time periods;

over the consecutive main time period, the one of the first and second main processors executes a second sequenced task;

wherein the method comprises;

a step of emission by the one of the first and second main processors of a coordination marker to the auxiliary processor at the start of each main time period;

a step of emission by the auxiliary processor of a response word formed on the basis of the last coordination marker received from the one of the first and second main processors at the end of each auxiliary time period;

a step of validation by the one of the first and second main processors of the response word received with respect to the first coordination marker emitted, the validation step being carried out at the start of the consecutive main time period before the emission of a new coordination marker; and

a step of signaling by the one of the first and second main processors if the response word received is not valid so as to signal a defect of coordination of the auxiliary processor.