Word line-dependent ramping of pass voltage and program voltage for three-dimensional memory

• US 9,466,369 B1
• Filed: 12/21/2015
• Issued: 10/11/2016
• Est. Priority Date: 12/21/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Ren, Jingjian, Pang, Liang, Yuan, Jiahui, Dong, Yingda
• Primary Examiner(s): Le, Vu
• Application Number:
  US14/976,107
• Time in Patent Office: 295 Days
• Field of Search: 365/185.17, 365/185.19, 365/185.22, 365/185.24
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Techniques are provided for programming a three-dimensional memory device while minimizing over-programming and program disturb. When a selected word line is at the source-side of a set of word lines, a channel gradient is created in the channel adjacent to the selected word line when a program voltage is applied. The gradient generates hot carriers which can cause over-programming of memory cells connected to the selected word line. To reduce the amount of hot carriers, a ramp rate and/or duration of a first step up of the program voltage is reduced. When the selected word line is not at the source-side of the set of word lines, a baseline ramp rate and/or duration can be used. A ramp rate and/or duration of the voltage applied to unselected word lines can be reduced as well but by a lesser amount.

Claims

1. An apparatus, comprising:

a set of word lines;

a string comprising a set of data memory cells extending from a group of one or more source-side data memory cells at a source-side of the string to a drain-side data memory cell at a drain-side of the string, wherein the string is among a plurality of strings of memory cells; and

a control circuit, the control circuit, to perform a program loop for a selected data memory cell in the set of data memory cells in the string, where the selected data memory cell is connected to a selected word line in the set of word lines, is configured to provide one increase and then another increase in a voltage of the selected word line, wherein at least one of a rate or a duration of the one increase is lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

2. The apparatus of claim 1, wherein:

the rate of the one increase is lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

3. The apparatus of claim 2, wherein:

the control circuit is configured to increase a voltage of unselected word lines in the set of word lines concurrent with the one increase in the voltage of the selected word line at a rate which is higher than the rate of the one increase when the selected data memory cell is among the group of one or more source-side data memory cells in the string.

4. The apparatus of claim 1, wherein:

the duration of the one increase is smaller when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

5. The apparatus of claim 4, wherein:

the control circuit is configured to increase a voltage of unselected word lines in the set of word lines concurrent with the one increase in the voltage of the selected word line for a duration which is longer than the duration of the one increase when the selected data memory cell is among the group of one or more source-side data memory cells in the string.

6. The apparatus of claim 1, wherein:

a maximum level reached by the voltage of the selected word line due to the one increase is lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

7. The apparatus of claim 1, wherein:

the group of one or more source-side data memory cells in the string comprises a first data memory cell which is at a source-side of the string and a second data memory cell which is adjacent to the first data memory cell; and

the rate of the one increase comprises a first value when the selected memory cell is the first data memory cell and a second value, higher than the first value, when the selected memory cell is the second data memory cell.

8. The apparatus of claim 7, wherein:

the control circuit is configured to increase a voltage of unselected word lines in the set of word lines concurrent with the one increase in the voltage of the selected word line; and

a rate of the increase in the voltage of the unselected word lines is greater than the rate of the one increase when the selected memory cell is the first data memory cell and when the selected memory cell is the second data memory cell.

9. The apparatus of claim 1, wherein:

the rate of the one increase is relatively lower when a temperature is relatively higher.

10. The apparatus of claim 1, wherein:

the group of one or more source-side data memory cells in the string comprises no more than 10% of the data memory cells in the string.

11. The apparatus of claim 1, wherein:

the string extends vertically in a three-dimensional memory device; and

the string comprises a continuous polysilicon channel.

12. The apparatus of claim 1, wherein:

the group of one or more source-side data memory cells in the string is adjacent to a dummy memory cell at the source-side of the string;

the apparatus further comprises an unselected string of data memory cells extending from a group of one or more source-side data memory cells at a source-side of the unselected string to a drain-side data memory cell at a drain-side of the unselected string, wherein each word line in the set of word lines is connected to a respective data memory cell in the selected string and to a respective data memory cell in the unselected string; and

the group of one or more source-side data memory cells in the unselected string is adjacent to a dummy memory cell at the source-side of the unselected string.

13. The apparatus of claim 1, wherein:

the another increase causes the voltage of the selected word line to reach a peak level in the program loop; and

the rate is relatively lower when the peak level is relatively higher.

14. The apparatus of claim 1, wherein:

the set of word lines extend in multiple sub-blocks of memory cells;

the control circuit is configured to program the sub-blocks in a sub-block programming order; and

the rate is relatively lower when the string is in a sub-block which is programmed relatively later in the sub-block programming order.

15. The apparatus of claim 1, wherein:

a rate of the another increase is lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

16. A method, comprising:

providing one increase in a voltage of a selected word line in a set of word lines, the selected word line is connected to a selected data memory cell in a string; and

after the one increase, providing another increase in the voltage of the selected word line, wherein a rate of the one increase is lower when the selected data memory cell is among a group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

17. The method of claim 16, wherein:

the one increase and the another increase are provided in each program loop of a plurality of program loops of a programming operation.

18. The method of claim 16, wherein:

the group of one or more source-side data memory cells in the string comprises a first data memory cell which is at a source-side of the string and a second data memory cell which is adjacent to the first data memory cell in the string; and

the rate of the one increase comprises a first value when the selected memory cell is the first data memory cell and a second value, higher than the first value, when the selected memory cell is the second data memory cell.

19. The method of claim 16, wherein:

a maximum level reached by the voltage of the selected word line due to the one increase is relatively lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

20. An apparatus, comprising:

means for providing one increase in a voltage of a selected word line in a set of word lines, the selected word line is connected to a selected data memory cell in a string; and

means for, after the one increase, providing another increase in the voltage of the selected word line, wherein at least one of a rate or a duration of the one increase is relatively lower when the selected data memory cell is among a group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.

21. The apparatus of claim 20, wherein:

a rate of the another increase is lower when the selected data memory cell is among the group of one or more source-side data memory cells in the string than when the selected data memory cell is not among the group of one or more source-side data memory cells in the string.