Method and device for processing an erase counter

• US 9,466,377 B2
• Filed: 02/26/2014
• Issued: 10/11/2016
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kho, Rex, Neal, Mathew
• Primary Examiner(s): OBERLY, ERIC T
• Application Number:
  US14/190,265
• Publication Number:
  US 20150243359A1
• Time in Patent Office: 958 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory.

Claims

1. A method for processing an erase counter comprising erase counter fields, the method comprising:

determining an unused erase counter field;

writing a selection code and an address information in the unused erase counter field, the selection code being indicative that one or more corresponding bits of the address information are;

defined by multiple bit values in a first operation, wherein, in the first operation, a value of the selection code indicates that a corresponding bit of the address information may be either “

0”

or “

1”

; and

defined by single bit values in a second operation, wherein, in the second operation, a value of the selection code indicates that a corresponding bit of the address information remains unchanged;

aligning the selection code at a least significant bit with the address information; and

combining the selection code and the address information to determine at least one physical address of a memory that is subject to an erase operation.

2. The method according to claim 1, wherein the physical address of the memory is directed to a sector or to a page of the memory.

3. The method according to claim 2, wherein at least one sector or at least one page of the memory is subject to the erase operation.

4. The method according to claim 3, wherein the erase operation is triggered or conducted prior to said processing of the erase counter or after said processing of the erase counter.

5. The method according to claim 1, wherein the selection code and the address information are combined to determine several physical addresses of the memory.

6. The method according to claim 1, wherein the selection code determines one or several physical addresses within the address information.

7. The method according to claim 1, wherein the first value is “

0” and

the second value is “

1”

.

8. The method according to claim 1, wherein determining an unused erase counter field comprises conducting a search operation for the unused erased counter field in an erase counter storage provided for the erase counter.

9. The method according to claim 1, wherein the erase counter is incremented by writing the selection code and the address information to the unused erase counter field.

10. The method according to claim 1, wherein the erase counter is associated with a portion of the memory, in particular a non-volatile memory, and wherein the erase operation applied to said portion of the memory triggers incrementing the erase counter.

11. The method according to claim 1, wherein the erase counter is part of a non-volatile memory, wherein the memory of the erase counter is not accessible or read-only to an application software.

12. The method according to claim 1, wherein each bit of the erase counter field is defined by a plurality of bits, wherein a majority decision is made based on the plurality of bits for the corresponding bit.

13. The method according to claim 1, the method further comprising:

reading the erase counter and storing it in a register;

searching for the unused erase counter field;

writing the selection code and the address information in the unused erase counter field; and

writing the register back to the erase counter.

14. The method according to claim 13, comprising:

indicating a warning or an error in case writing the register back to the erase counter was not successful.

22. A computer program product embodied on a non-transitory computer-readable medium comprising software code stored thereon, when executed, cause a processor to perform the method according to claim 1.

15. A device comprising:

an erase counter comprising several erase counter fields; and

a processor configured to;

determine an unused erase counter field;

write a selection code and an address information in the unused erase counter field, the selection code being indicative that one or more corresponding bits of the address information are;

defined by multiple bit values in a first operation, wherein, in the first operation, a value of the selection code indicates that a corresponding bit of the address information may be either “

0”

or “

1”

; and

defined by single bit values in a second operation, wherein, in the second operation, a value of the selection code indicates that a corresponding bit of the address information remains unchanged;

align the selection code at a least significant bit with the address information; and

combine the selection code and the address information to determine at least one physical address of a memory that is subject to an erase operation.

16. The device according to claim 15, wherein the memory comprises a memory portion, and wherein the processor is configured to process the erase counter based on the erase operation to be conducted on the memory portion.

17. The device according to claim 15, wherein the processor is further configured to:

read the erase counter and storing it in a register;

search for the unused erase counter field;

write the selection code and the address information in the unused erase counter field; and

write the register back to the erase counter.

18. The device according to claim 15, wherein the device is implemented on a single chip or die.

19. The device according to claim 15, wherein the memory portion is part of a non-volatile memory.

20. The device according to claim 15, wherein the memory portion comprises at least one of the following:

floating gate cells;

PCRAM,

RRAM,

MRAM,

MONOS devices,

nano crystal cells,

FeRAM,

hard drive, and

non-volatile storage.

21. A device for processing an erase counter comprising erase counter fields, the device comprising:

means for determining an unused erase counter field;

means for writing a selection code and an address information in the unused erase counter field, the selection code being indicative that one or more corresponding bits of the address information are;

defined by multiple bit values in a first operation, wherein, in the first operation, a value of the selection code indicates that a corresponding bit of the address information may be either “

0”

or “

1”

; and

defined by single bit values in a second operation, wherein, in the second operation, a value of the selection code indicates that a corresponding bit of the address information remains unchanged;

means for aligning the selection code at a least significant bit with the address information; and

means for combining the selection code and the address information to determine at least one physical address of a memory.