Substrate comprising improved via pad placement in bump area

• US 9,466,578 B2
• Filed: 04/11/2014
• Issued: 10/11/2016
• Est. Priority Date: 12/20/2013
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Fu, Jie, Aldrete, Manuel, Shah, Milind Pravin
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): Rundio, Regan J
• Application Number:
  US14/251,518
• Publication Number:
  US 20150179590A1
• Time in Patent Office: 914 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0903 Bonding areas having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/0912 Layout layout of bonding areas prior to the connecting process H01L2224/0612
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Claims

1. An integrated device comprising:

a substrate;

a plurality of vias traversing the substrate, a first via of the plurality of vias having a first via dimension; and

a first bump pad coupled to a first end of a first via, wherein the first bump pad has a first pad dimension that is equal to or less than the first via dimension;

a plurality of interconnects on the substrate;

wherein the plurality of vias are co-planar and arranged in rows and columns;

wherein, for at least a row of vias of the plurality of vias, only one respective interconnect of the plurality of interconnects is located between each pair of vias in the row.

2. The integrated device of claim 1, further comprising:

a second via traversing the substrate, wherein the second via has a second via dimension; and

a second bump pad coupled to a second end of a second via, wherein the second bump pad has a second pad dimension that is equal to or less than the second via dimension.

3. The integrated device of claim 2, wherein a pitch between the first via and the second via is about 80 microns (μ

m) or less.

4. The integrated device of claim 2, wherein a pitch between the first via and the second via is about 125 microns (μ

m) or less.

5. The integrated device of claim 1, wherein the first bump pad is configured to couple to an interconnect of a die.

6. The integrated device of claim 1, wherein the first bump pad is a peripheral bump pad that is located adjacent to an edge of a die area of the substrate.

7. The integrated device of claim 1, wherein the first bump pad is configured to couple to a first bump from a die.

8. The integrated device of claim 7, wherein the first bump includes a first under metallization (UBM) layer, a first interconnect pillar, and a first solder ball.

9. The integrated device of claim 1, wherein the substrate comprises one of at least a dielectric, glass, ceramic, and/or silicon.

10. The integrated device of claim 1, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

11. The integrated device of claim 1, wherein the first via is filled with a metal across an entirety of the first via dimension.

12. The integrated device of claim 1, wherein the first pad dimension is a pad width and the first via dimension is a via width and an interface between the first bump pad and the first via is co-planar with a surface of the substrate.

13. The integrated device of claim 1, wherein the plurality of interconnects include additional bump pads coupled to respective traces.

14. The integrated device of claim 1, wherein, for at least a column of vias of the plurality of vias, only one respective interconnect of the plurality of interconnects is located between each pair of vias in the column.

15. A method for fabricating an integrated device, comprising:

forming a substrate;

forming a plurality of vias traversing the substrate, a first via of the plurality of vias having a first via dimension;

forming a first bump pad on a first end of the first via such that the first bump pad is coupled to the first via, wherein the first bump pad has a first pad dimension that is equal to or less than the first via dimension;

forming a plurality of interconnects on the substrate; and

arranging the plurality of vias in rows and columns such that for at least a row of vias of the plurality of vias, only one respective interconnect of the plurality of interconnects is located between each pair of vias in the row;

wherein the plurality of vias are co-planar.

16. The method of claim 15, further comprising:

forming a second via traversing the substrate, wherein the second via has a second via dimension; and

forming a second bump pad on a second end of the second via such that the second bump pad is coupled to the second via, wherein the second bump pad has a second pad dimension that is equal to or less than the second via dimension.

17. The method of claim 16, wherein a pitch between the first via and the second via is about 80 microns (μ

m) or less.

18. The method of claim 16, wherein a pitch between the first via and the second via is about 125 microns (μ

m) or less.

19. The method of claim 15, wherein the first bump pad is configured to couple to an interconnect of a die.

20. The method of claim 15, wherein the first bump pad is a peripheral bump pad that is located adjacent to an edge of a die area of the substrate.

21. The method of claim 15, wherein the first bump pad is configured to couple to a first bump from a die.

22. The method of claim 21, wherein the first bump includes a first under metallization (UBM) layer, a first interconnect pillar, and a first solder ball.

23. The method of claim 15, wherein the substrate comprises one of at least a dielectric, glass, ceramic, and/or silicon.

24. The method of claim 15, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

25. The method of claim 15, further comprising:

filling the first via with a metal across an entirety of the first via dimension.

26. The method of claim 15, wherein the first pad dimension is a pad width and the first via dimension is a via width and an interface between the first bump pad and the first via is co-planar with a surface of the substrate.

27. The method of claim 15, wherein the plurality of interconnects include additional bump pads coupled to respective traces.

28. The method of claim 15, wherein, for at least a column of vias of the plurality of vias, only one respective interconnect of the plurality of interconnects is located between each pair of vias in the column.