Geometry of MOS device with low on-resistance

• US 9,466,596 B2
• Filed: 12/26/2007
• Issued: 10/11/2016
• Est. Priority Date: 12/28/2006
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Krishnamoorthy, Ravishanker
• Primary Examiner(s): Li, Meiya
• Application Number:
  US11/964,696
• Publication Number:
  US 20080157195A1
• Time in Patent Office: 3,212 Days
• Field of Search: 257/337, 257/341, 257/343, 257/355, 257/356, 257/360, 257/401, 257/E23.153, 257/E29.013, 257/E29.027, 257/E29.116, 257/E29.118, 257/E28.121, 257/E29.146, 257/E29.255, 257/E29.256
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

Claims

1. A Metal Oxide Semiconductor (MOS) device formed on a substrate, the MOS device comprising:

a drain region, wherein the drain region has a shape of a rectangle or a square;

a gate region (i) surrounding the drain region and (ii) formed in a closed loop around the drain region, wherein the closed loop has a shape corresponding to the shape of the drain region;

a plurality of source regions (i) arranged around the gate region and (ii) across from the drain region; and

a plurality of bulk regions arranged around the gate region,

wherein a first source region of the plurality of source regions comprises a first side that (i) faces the drain region and (ii) has a first maximum width,

wherein a second source region of the plurality of source regions comprises a first side that (i) faces the drain region and (ii) has a second maximum width, the second maximum width being substantially different from the first maximum width,

wherein the first maximum width of the first side of the first source region is substantially equal to a maximum width of the gate region,

wherein the second maximum width of the first side of the second source region is substantially equal to a maximum width of the drain region, and

wherein the maximum width of the gate region is different from the maximum width of the drain region.

2. The MOS device of claim 1, wherein:

the substrate has a shape corresponding to the shape of the drain region; and

each bulk region of the plurality of bulk regions is arranged in a corresponding corner of the substrate.

3. The MOS device of claim 1, wherein a channel region is formed beneath the gate region.

4. The MOS device of claim 3, wherein the channel region is configured so that current flows from each source region to the drain region.

5. The MOS device of claim 1, wherein the MOS device is a transistor.

6. The MOS device of claim 1, wherein the substrate is a silicon substrate, and the gate region includes polysilicon.

7. The MOS device of claim 6, wherein the MOS device is a Square Double-Diffused Metal Oxide Semiconductor (SQDMOS).

8. The MOS device of claim 1, wherein:

the drain region includes a first drain region contact;

at least one of the source regions includes a first source region contact; and

a distance between (i) the first drain region contact and (ii) the gate region is greater than a distance between (i) the first source region contact and (ii) the gate region.

9. The MOS device of claim 1, wherein:

each bulk region of the plurality of bulk regions separates two corresponding source region of the plurality of source regions.

10. The MOS device of claim 1, wherein:

the plurality of source regions comprises (i) the first source region, (ii) the second source region, (iii) a third source region, and (iv) a fourth source region;

the drain region has (i) a first side, (ii) a second side that is perpendicular to the first side, (iii) a third side that is opposite to and parallel to the first side, and (iv) a fourth side that is opposite to and parallel to the second side;

the first source region, the second source region, the third source region, and the fourth source region are arranged facing the first side, the second side, the third side, and the fourth side, respectively, of the drain region;

the third source region comprises a first side that (i) faces the drain region and (ii) has a third maximum width, wherein the third maximum width of the first side of the third source region is substantially equal to the first maximum width of the first side of the first source region; and

the fourth source region comprises a first side that (i) faces the drain region and (ii) has a fourth maximum width, wherein the fourth maximum width of the first side of the fourth source region is substantially equal to the second maximum width of the first side of the second source region.

11. The MOS device of claim 1, wherein:

each of the plurality of source regions has a shape of a rectangle.