Semiconductor device including multiple fin heights

• US 9,466,702 B1
• Filed: 12/09/2015
• Issued: 10/11/2016
• Est. Priority Date: 12/09/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Karthik, Cheng, Kangguo, Hashemi, Pouya, Reznicek, Alexander
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US14/963,603
• Time in Patent Office: 307 Days
• Field of Search: 438268-272, 438/424
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a substrate, an base layer disposed on the substrate having a thickness C in first area and a thickness B in a second area and a hole extending to the substrate filled with semiconductor, a first semiconductor fin disposed on the first area and having a height A, and a second semiconductor fin disposed on the second area and having a height D, wherein (A+C)=(B+D).

Claims

1. A method of making a semiconductor device comprising:

forming a mask on a portion of a base layer covering a substrate;

removing a portion of the base layer from the unmasked region such that the base layer has at least two thicknesses;

removing the mask from the base layer having at least two thicknesses;

forming a hole in the base layer to reveal the substrate;

depositing a sacrificial material over the base layer having two thicknesses and a hole;

planarizing the sacrificial material;

patterning and etching the sacrificial material to define active areas comprising the hole;

disposing a dielectric material over the patterned and etched sacrificial material;

patterning and etching the dielectric material to form trenches to the base layer on two opposing sides of the active area, wherein the trenches are adjacent to the sacrificial material;

removing the sacrificial material beneath the dielectric material to form a cavity bounded by the trenches and comprising the hole;

forming a semiconductor layer in the cavity on the base layer having two thicknesses by epitaxial lateral overgrowth;

removing the dielectric material to expose the semiconductor layer; and

patterning and etching the semiconductor layer to form a first fin having a first height and a second fin having a second height.

2. The method of claim 1 wherein the base layer comprises silicon oxide and the substrate layer comprises silicon.

3. The method of claim 1 wherein the sacrificial material comprises silicon nitride.

4. The method of claim 1, wherein 5 to 90% of the base layer'"'"'s thickness is removed.

5. The method of claim 1, further comprising forming a second mask on a portion of the base layer having at least two thicknesses and etching the unmasked area.

6. The method of claim 1, wherein the base layer comprises silicon oxide, the dielectric material comprises silicon boro carbo nitride and the sacrificial material comprises silicon nitride.

7. The method of claim 1, wherein the dielectric material comprises silicon oxide, silicon nitride (SiN), silicon oxide carbonitride (SiOCN), silicon boro carbo nitride (SiBCN), spin-on glass, flowable oxide, high density plasma oxide, borophosphosilicate glass, oxides, nitrides, or oxynitrides.

8. The method of claim 1, wherein the semiconductor layer comprises silicon, silicon-germanium, III-V materials, or a combination of two or more of the foregoing.

9. The method of claim 1, wherein epitaxial lateral overgrowth is achieved by metal organic chemical vapor deposition, metal organic vapor phase epitaxy, plasma enhanced chemical vapor deposition, remote plasma enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, or liquid phase epitaxy.

10. A method of making a semiconductor device comprising:

forming a mask on a portion of a base layer comprising silicon oxide covering a substrate comprising silicon;

removing a portion of the base layer from the unmasked region such that the base layer has two thicknesses;

removing the mask from the base layer having two thicknesses;

forming at least one hole in the base layer to reveal the substrate;

depositing a sacrificial material comprising silicon nitride over the base layer having two thicknesses and at least one hole;

planarizing the sacrificial material;

patterning and etching the sacrificial material to provide an active area comprising the hole;

disposing a dielectric material comprising SiOCN, SiBCN, or a combinations there of over the patterned and etched sacrificial material;

patterning and etching the dielectric material to form trenches to the base layer on at least two opposing sides of the active area, wherein the trenches are adjacent to the sacrificial material;

removing the sacrificial material beneath the dielectric material to form a cavity bounded by the trenches and comprising the hole;

forming a semiconductor layer comprising InGaAs in the cavity on the base layer, wherein the semiconductor layer has two thicknesses;

removing the dielectric material to expose the semiconductor layer; and

patterning and etching the semiconductor layer to form a first fin having a first height and a second fin having a second height.

11. The method of claim 10, wherein 5 to 90% of the base layer'"'"'s thickness is removed.

12. The method of claim 10, further comprising forming a second mask on a portion of the base layer having two thicknesses and etching the unmasked area to form a base layer having three thicknesses.

13. The method of claim 10, wherein planarizing is performed using chemical mechanical planarization.