Source and body contact structure for trench-DMOS devices using polysilicon

• US 9,466,710 B2
• Filed: 11/12/2015
• Issued: 10/11/2016
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hbert, Franois, Bhalla, Anup
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/939,106
• Publication Number:
  US 20160079414A1
• Time in Patent Office: 334 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a dielectric disposed on top of the gate electrode, and a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device comprising:

a body region formed in an epitaxial layer;

a gate electrode formed in a trench in the body region and epitaxial layer;

a source region disposed on the body region next to the gate electrode;

a gate oxide disposed between the gate electrode and the source region, the body region and the epitaxial layer;

a drain region formed by a substrate disposed below a bottom of the gate electrode and below the body region;

an dielectric disposed on top of the gate electrode;

a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric, wherein the doped polysilicon spacer has a dopant concentration higher than a dopant concentration of the source region; and

a source metal layer disposed on the device such that the doped polysilicon spacer is in electrical contact with the source region and the source metal layer.

2. The semiconductor device of claim 1, wherein a portion of a top surface of the body region not underlying the source region is recessed to a lower level than a portion of the top surface of the body region underlying the source region.

3. The semiconductor device of claim 1, wherein the doped polysilicon spacer extends to a top portion of the source region.

4. The semiconductor device of claim 1, wherein the semiconductor device is an N-channel device.

5. The semiconductor device of claim 1 wherein the doped polysilicon spacer is formed on a shelf on a portion of a top surface of the source region that is not covered by the dielectric wherein the shelf is configured such that the doped polysilicon spacer contacts the top source region on a horizontal surface as well as a vertical surface.

6. The semiconductor device of claim 1 further comprising a barrier metal disposed on top of the doped polysilicon spacer and the dielectric.

7. The semiconductor device of claim 1 wherein the N+ polysilicon spacer extends to a top portion of the source region.

8. The semiconductor device of claim 1, wherein the dielectric is an oxide.

9. The semiconductor device of claim 8 wherein the oxide is a reflowed oxide.

10. The semiconductor device of claim 1 wherein the source region is an N-source.