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Dual-SiGe epitaxy for MOS devices

  • US 9,466,716 B2
  • Filed: 05/28/2010
  • Issued: 10/11/2016
  • Est. Priority Date: 12/05/2006
  • Status: Active Grant
First Claim
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1. A method for forming a semiconductor structure, the method comprising:

  • forming a gate stack on a semiconductor substrate, the gate stack comprising a gate electrode formed over a gate dielectric layer;

    forming a pair of lightly doped source/drain (LDD) regions in the semiconductor substrate adjacent to and opposing the gate stack;

    after forming the pair of LDD regions, forming a first pair of gate spacers disposed on opposing sidewalls of the gate stack, the first pair of gate spacers at least partially covering the pair of LDD regions;

    forming a second pair of gate spacers on top surfaces of the pair of LDD regions and on the opposing sidewalls of the first pair of gate spacers;

    forming in the semiconductor substrate, a pair of first recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a first distance;

    forming in the semiconductor substrate, a pair of second recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a second distance less than the first distance; and

    after forming the pair of first recesses and the pair of second recesses, forming a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein forming the stressor comprises;

    epitaxially forming a pair of opposing first stressor regions spaced from the gate stack using a first flow rate of a Ge-containing precursor gas while doping to a first p-type impurity concentration; and

    epitaxially forming a pair of opposing second stressor regions on the pair of opposing first stressor regions and partially underlying the gate stack, the pair of opposing second stressor regions formed by using a second flow rate of the Ge-containing precursor gas while doping to a second p-type impurity concentration, wherein the pair of opposing second stressor regions extends laterally closer to a channel region underlying the gate stack than the pair of opposing first stressor regions, wherein, a first Ge concentration of the pair of opposing first stressor regions is different than a second Ge concentration of the pair of opposing second stressor regions.

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