Dual-SiGe epitaxy for MOS devices

• US 9,466,716 B2
• Filed: 05/28/2010
• Issued: 10/11/2016
• Est. Priority Date: 12/05/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yin-Pin
• Primary Examiner(s): Li, Meiya
• Application Number:
  US12/790,304
• Publication Number:
  US 20100240186A1
• Time in Patent Office: 2,328 Days
• Field of Search: 257/19, 257/E21.43, 257/E21.431, 257/E21.438, 257/E29.085, 257/E29.266, 257/E21.085, 257/E21.09, 257/E21.092, 257/E21.1, 257/E21.102, 257/E21.106, 257/E21.115, 257/E21.131, 438/185, 438/226, 438/231, 438/247, 438/300, 438/301, 438/305
• US Class Current: 1/1
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Claims

1. A method for forming a semiconductor structure, the method comprising:

forming a gate stack on a semiconductor substrate, the gate stack comprising a gate electrode formed over a gate dielectric layer;

forming a pair of lightly doped source/drain (LDD) regions in the semiconductor substrate adjacent to and opposing the gate stack;

after forming the pair of LDD regions, forming a first pair of gate spacers disposed on opposing sidewalls of the gate stack, the first pair of gate spacers at least partially covering the pair of LDD regions;

forming a second pair of gate spacers on top surfaces of the pair of LDD regions and on the opposing sidewalls of the first pair of gate spacers;

forming in the semiconductor substrate, a pair of first recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a first distance;

forming in the semiconductor substrate, a pair of second recesses adjacent the opposing sidewalls of the gate stack and spaced apart from the opposing sidewalls of the gate stack by a second distance less than the first distance; and

after forming the pair of first recesses and the pair of second recesses, forming a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein forming the stressor comprises;

epitaxially forming a pair of opposing first stressor regions spaced from the gate stack using a first flow rate of a Ge-containing precursor gas while doping to a first p-type impurity concentration; and

epitaxially forming a pair of opposing second stressor regions on the pair of opposing first stressor regions and partially underlying the gate stack, the pair of opposing second stressor regions formed by using a second flow rate of the Ge-containing precursor gas while doping to a second p-type impurity concentration, wherein the pair of opposing second stressor regions extends laterally closer to a channel region underlying the gate stack than the pair of opposing first stressor regions, wherein, a first Ge concentration of the pair of opposing first stressor regions is different than a second Ge concentration of the pair of opposing second stressor regions.

2. The method of claim 1, wherein:

forming the pair of opposing first stressor regions comprises epitaxially growing the pair of opposing first stressor regions in the pair of first recesses; and

forming the pair of opposing second stressor regions comprises epitaxially growing the pair of opposing second stressor regions in the pair of second recesses.

3. The method of claim 1, wherein forming the pair of first recesses and forming the pair of second recesses further comprise:

forming one of the pair of first recesses along a sidewall of one of the second pair of gate spacers;

removing the one of the second pair of gate spacers; and

forming one of the pair of second recesses along the sidewall of the one of the first pair of gate spacers and partially underlying the gate stack, wherein the one of the pair of second recesses is substantially shallower than the one of the pair of first recesses.

4. The method of claim 1, wherein the pair of opposing first stressor regions has a first atomic percentage of germanium to germanium and silicon, the pair of opposing second stressor regions has a second atomic percentage of germanium to germanium and silicon, and the second atomic percentage of germanium to germanium and silicon is higher than the first atomic percentage of germanium to germanium and silicon.

5. The method of claim 4, wherein the first atomic percentage of germanium to germanium and silicon is between about 15 percent and about 25 percent, and wherein the second atomic percentage of germanium to germanium and silicon is between about 25 percent and about 40 percent.

6. The method of claim 1, wherein the second flow rate is greater than the first flow rate.

7. The method of claim 1, wherein the first p-type impurity concentration is higher than the second p-type impurity concentration.

8. A method of forming a semiconductor structure, the method comprising:

forming a gate stack on a semiconductor substrate, the gate stack comprising a gate electrode overlying a gate dielectric layer;

forming a lightly doped drain (LDD) region in the semiconductor substrate and adjacent to a sidewall of the gate stack;

after forming the LDD region, forming a gate spacer on the sidewall of the gate stack;

forming a disposable spacer on a sidewall of the gate spacer, wherein a bottom surface of the disposable spacer is on a top surface of the LDD region;

forming a first recess along a sidewall of the disposable spacer;

removing the disposable spacer;

forming a second recess along the sidewall of the gate spacer and partially underlying the gate spacer, wherein the second recess is substantially shallower than the first recess;

after forming the first recess and the second recess, forming a first silicon germanium (SiGe) region that substantially fills the first recess using a first germane (GeH₄) gas flow rate while doping a first p-type dopant at a first p-type impurity concentration; and

after forming the first SiGe region, forming a second SiGe region that substantially fills the second recess using a second GeH₄ gas flow rate while doping a second p-type dopant at a second p-type impurity concentration;

wherein;

the second GeH₄ gas flow rate is different than the first GeH₄ gas flow rate;

the second p-type impurity concentration is different than the first p-type impurity concentration; and

the second SiGe region has a germanium concentration different than the first SiGe region.

9. The method of claim 8, wherein the second SiGe region has a higher germanium concentration than the first SiGe region.

10. The method of claim 9, wherein the second GeH₄ gas flow rate is higher than the first GeH₄ gas flow rate.

11. The method of claim 8, further comprising implanting the second p-type dopant into the second SiGe region after forming the first SiGe region and the second SiGe region.

12. The method of claim 8, wherein the first p-type impurity concentration in the first SiGe region is between about 5×

10²⁰/cm³ and about 1×

10²¹/cm³, and the second p-type impurity concentration in the second SiGe region is between about 1×

10¹⁹/cm³ and about 5×

10²⁰/cm³.

13. The method of claim 8, wherein the second p-type impurity concentration is lower than the first p-type impurity concentration.

14. A method of forming a transistor, the method comprising:

providing a semiconductor substrate;

forming a gate stack on the semiconductor substrate, the gate stack comprising a gate electrode overlying a gate dielectric layer, the gate stack having a first sidewall and a second sidewall, the second sidewall opposing the first sidewall;

forming;

opposing lightly doped source/drain (LDD) regions in the semiconductor substrate adjacent to the first sidewall and the second sidewall;

after forming the opposing LDD regions, a first gate spacer on the first sidewall of the gate stack; and

a second gate spacer on the second sidewall of the gate stack, wherein, the first gate spacer has a first vertical gate spacer sidewall, and the second gate spacer has a second vertical gate spacer sidewall;

forming;

a first disposable spacer on the first vertical gate spacer sidewall; and

a second disposable spacer on the second vertical gate spacer sidewall, wherein, the first disposable spacer has a first vertical disposable spacer sidewall, the second disposable spacer has a second vertical disposable spacer sidewall, and bottom surfaces of the first disposable spacer and the second disposable spacer are on top surfaces of the opposing LDD regions respectively;

forming a first recess on one side of the gate stack and forming a second recess on an opposing side of the gate stack, the first recess being spaced from the gate stack along the first vertical disposable spacer sidewall, and the second recess being spaced from the gate stack along the second vertical disposable spacer sidewall;

removing the first disposable spacer and the second disposable spacer;

forming a third recess on at least a portion of the first recess, the third recess underlying a portion of the first gate spacer, and forming a fourth recess on at least a portion of the second recess, the fourth recess underlying a portion of the second gate spacer, the third recess formed along the first vertical gate spacer sidewall, and the fourth recess formed along the second vertical gate spacer sidewall, wherein the third recess is substantially shallower than the first recess, and the fourth recess is substantially shallower than the second recess;

after forming the third recess and the fourth recess, forming a first SiGe region that substantially fills the first recess and a second SiGe region that substantially fills the second recess, wherein the first SiGe region and the second SiGe region are formed by epitaxial growth with a first precursor gas introduced at a first precursor gas flow rate while doping a first p-type impurity at a first p-type impurity concentration; and

after forming the first SiGe region and the second SiGe region, forming a third SiGe region that substantially fills the third recess and a fourth SiGe region that substantially fills the fourth recess, wherein the third SiGe region and the fourth SiGe region are formed by epitaxial growth with a second precursor gas introduced at a second precursor gas flow rate that is higher than the first precursor gas flow rate, and while doping a second p-type impurity at a second p-type impurity concentration that is lower than the first p-type impurity concentration, wherein a first Ge concentration of the first SiGe region and the second SiGe region is different than a second Ge concentration of the third SiGe region and the fourth SiGe region.

15. The method of claim 14, wherein the first SiGe region in the first recess and the third SiGe region in the third recess form a source/drain of the transistor, and the second SiGe region in the second recess and the fourth SiGe region in the fourth recess form a drain/source of the transistor.

16. The method of claim 14, wherein the third SiGe region has a higher concentration of germanium to germanium and silicon than a first concentration of germanium to germanium and silicon of the first SiGe region, and the fourth SiGe region has a higher concentration of germanium to germanium and silicon than a second concentration of germanium to germanium and silicon of the second SiGe region.

17. The method of claim 14, further comprising implanting an additional p-type impurity into the third SiGe region and the fourth SiGe region after the steps of forming the third SiGe region and the fourth SiGe region.

18. The method of claim 14, wherein the first p-type impurity concentration is between about 5×

10²⁰/cm³ and about 1×

10²¹/cm³, and the second p-type impurity concentration is between about 1×

10¹⁹/cm³ and about 5×

10²⁰/cm³.

19. The method of claim 14, wherein at least one of the first precursor gas or the second precursor gas comprises GeH₄.

20. The method of claim 14, wherein at least one of the first p-type impurity and the second p-type impurity comprises boron.