Semiconductor device and method for manufacturing the same

• US 9,466,726 B2
• Filed: 04/23/2015
• Issued: 10/11/2016
• Est. Priority Date: 09/29/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Hayakawa, Masahiko, Shinohara, Satoshi
• Primary Examiner(s): Such, Matthew W.
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/694,166
• Publication Number:
  US 20150228800A1
• Time in Patent Office: 537 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. The taper angle θ of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.

Claims

1. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating film over the gate electrode layer;

an oxide semiconductor film comprising a channel formation region over the gate insulating film;

an insulating layer over and in contact with the oxide semiconductor film;

a source electrode layer having an end portion over the insulating layer; and

a drain electrode layer having an end portion over the insulating layer,

wherein the end portion of the source electrode layer and the end portion of the drain electrode layer overlap with the channel formation region,

wherein the source electrode layer is in direct contact with a surface of the oxide semiconductor film through a first opening,

wherein the drain electrode layer is in direct contact with the surface of the oxide semiconductor film through a second opening,

wherein the first opening comprises a first portion and a second portion,

wherein the first portion of the first opening overlaps with the gate electrode layer and the second portion of the first opening does not overlap with the gate electrode layer, and

wherein an angle between a side surface of an end portion of the insulating layer and the insulating surface is smaller than or equal to 60°

.

2. The semiconductor device according to claim 1, wherein a thickness of the insulating layer is less than or equal to 0.3 μ

m.

3. The semiconductor device according to claim 1, wherein the end portion of the drain electrode layer overlaps with a top surface of the insulating layer.

4. The semiconductor device according to claim 1, wherein the end portion of the drain electrode layer overlaps with a side surface of the end portion of the insulating layer.

5. The semiconductor device according to claim 1, wherein a cross-sectional shape of the insulating layer is a trapezoid.

6. The semiconductor device according to claim 1, wherein a cross-sectional shape of the insulating layer is a triangle.

7. The semiconductor device according to claim 1, wherein at least part of a cross-sectional shape of the insulating layer is curved.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises at least one selected from the group consisting of indium, gallium, and zinc.

9. A display module comprising the semiconductor device according to claim 1, comprising at least one of an FPC and a housing.

10. An electronic device comprising the semiconductor device according to claim 1, comprising at least one of a display portion, a battery, and an operation key.

11. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating film over the gate electrode layer;

an oxide semiconductor film comprising a channel formation region over the gate insulating film;

an insulating layer over and in contact with the oxide semiconductor film;

a source electrode layer having an end portion over the insulating layer; and

a drain electrode layer having an end portion over the insulating layer,

wherein the end portion of the source electrode layer and the end portion of the drain electrode layer overlap with the channel formation region,

wherein the source electrode layer is in direct contact with a surface of the oxide semiconductor film through a first opening,

wherein the drain electrode layer is in direct contact with the surface of the oxide semiconductor film through a second opening,

wherein the first opening comprises a first portion and a second portion,

wherein the first portion of the first opening overlaps with the gate electrode layer and the second portion of the first opening does not overlap with the gate electrode layer,

wherein an angle between a side surface of an end portion of the insulating layer and the insulating surface is smaller than or equal to 60°

, and

wherein a thickness of the insulating layer is less than or equal to 0.3 μ

m.

12. The semiconductor device according to claim 11, wherein the thickness of the insulating layer is greater than or equal to 5 nm and less than or equal to 0.1 μ

m.

13. The semiconductor device according to claim 11, wherein the end portion of the drain electrode layer overlaps with a top surface of the insulating layer.

14. The semiconductor device according to claim 11, wherein the end portion of the drain electrode layer overlaps with the side surface of the end portion of the insulating layer.

15. The semiconductor device according to claim 11, wherein a cross-sectional shape of the insulating layer is a trapezoid.

16. The semiconductor device according to claim 11, wherein a cross-sectional shape of the insulating layer is a triangle.

17. The semiconductor device according to claim 11, wherein at least part of a cross-sectional shape of the insulating layer is curved.

18. The semiconductor device according to claim 11, wherein the oxide semiconductor film comprises at least one selected from the group consisting of indium, gallium, and zinc.

19. A display module comprising the semiconductor device according to claim 11, comprising at least one of an FPC and a housing.

20. An electronic device comprising the semiconductor device according to claim 11, comprising at least one of a display portion, a battery, and an operation key.