Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

• US 9,466,790 B2
• Filed: 11/05/2015
• Issued: 10/11/2016
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Samachisa, George
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US14/933,672
• Publication Number:
  US 20160072058A1
• Time in Patent Office: 341 Days
• Field of Search: 365/51, 365/130, 365/185.11, 365/185.13, 365/63, 365/148, 365/174, 365/135, 365/139, 365/180, 365/185.05, 365/185.18, 365/189.011, 365/163, 365/185.06, 365/185.21
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/06035 Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/55 Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
• CPC Class Codes: G11C 2213/71 : Three dimensional array
• CPC Class Codes: G11C 2213/75 : Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/78 : Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 : between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/8822 : Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Claims

1. A re-programmable non-volatile semiconductor memory, comprising:

a plurality of planes stacked on top of one another over a semiconductor substrate, in each one of the planes, a plurality of word lines elongated in a x-direction and spaced apart in a y-direction across the plane;

a plurality of local bit lines extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the planes between the word lines in the y-direction, the word line and the local bit lines therefore crossing adjacent each other at a plurality of crossings in the plurality of planes, wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates;

a plurality of re-programmable non-volatile memory elements, each non-volatile memory element connected between a corresponding word line and corresponding local bit lines adjacent corresponding crossings, each non-volatile memory elements having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto;

a plurality of select devices formed in the substrates, each select device able to connect a corresponding one of the local bit lines to a corresponding one of global bines formed in the substrate;

word line select circuits for addressing one or more word line of one or more groups of the plurality of non-volatile memory elements to be reset; and

a control circuit formed in the substrate to connect, wherein in response to control signals, including addresses of one or more groups of the plurality of memory elements to be reset, selected ones of the plurality of local bit lines to the plurality of global bit lines in a manner that for each global bit line at least two local bit lines adjacent to each other are connected to said global bit line at a same time, said two local bit lines connected each via a single memory element to a same corresponding selected word line.

2. The memory of claim 1, wherein the plurality of global bit lines are elongated in the y-direction and spaced apart in the x-direction.

3. The memory of claim 1, wherein the memory elements are provided by layers of non-conductive material that individually extend continuously across multiple ones of the plurality of locations where the word lines and local bit lines cross adjacent each other.

4. The memory of claim 3, wherein the individual layers of non-conductive material extend continuously across multiple ones of the plurality of locations both across and within individual ones of the plurality of planes.

5. The memory of claim 3, wherein the individual layers of non-conductive material are sandwiched between the word lines and the local bit lines at individual ones of the plurality of locations where the word lines and local bit lines cross adjacent each other.

6. The memory of claim 1, wherein the memory elements include a plurality of pieces of material that contact the plurality of word lines on a surface facing in the z-direction, the plurality of pieces of material at the plurality of crossings of the word lines and local bit lines being discrete and electrically separated from one another.

7. The memory of claim 6, wherein the discrete pieces of material additionally contact the plurality of local bit lines on surfaces thereof facing the y-direction.

8. The memory of claim 6, wherein the discrete pieces of material additionally contact stubs of conductive material that individually contacts one of the plurality of local bit lines on a surface facing the y-direction and contacts one of the pieces of material on a surface facing the z-direction.

9. The memory of claim 6, wherein the pieces of material are characterized by being electrically conductive.

10. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which includes;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate,

a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions,

in each plane a plurality of word lines elongated in the x-direction across the planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of crossing across the planes,

a plurality of re-programmable non-volatile memory elements, each non-volatile memory element connected between a corresponding local bit lines and a corresponding word line crossing adjacent each other at an associated crossing of the plurality of locations, the memory elements being individually switchable between at least first and second stable electrically detectable states such that application of a first electrical stimuli thereto causes the memory element to switch from the first state to the second state and application of a second electrical stimuli thereto causes the memory element to switch from the second state to the first state, and

a plurality of select devices formed in the substrate, each select device connecting a corresponding one of the of the plurality of local bit lines to a corresponding one of a plurality of global bit lines in response to a corresponding one of selected control signals;

applying the select control signal to the plurality of select devices in order to connect corresponding local bit lines to corresponding global bit lines; and

causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected;

wherein applying the select control signals includes applying the select control signals to the plurality of select devices in order to connect a row of local bit lines to the global bit lines, said row being selected and extending in the x-direction; and

wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states includes simultaneously resetting to the first state two rows of memory elements associated with and connected to the selected row of local bit lines and along opposite sides thereof in the y-direction by applying the second electrical stimulus to the global bit lines and to two of the word lines adjacent the selected row of local bit lines on said opposite sides thereof.

11. The method of claim 10, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes subsequently programming data into one of the two rows of reset memory elements by applying the first electrical stimulus to a plurality of the global bit lines and one of the word lines adjacent the selected row of local bit lines on the side thereof of the one row of memory elements being programmed.

12. The method of claim 10, additionally comprising reading the states of a row of memory elements along one side in the y-direction of the selected row of local bit lines by applying reading electrical stimuli to the global bit lines and word lines such that the states of the memory elements are read from an electrical quantity appearing on the global bit lines.

13. The method of claim 10, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes applying a plurality of pulses of the one of the first and second stimuli and, in between successive pulses, verifying the state of the one or more of the plurality of memory elements.

14. The method of claim 13, wherein verifying the state of the one or more of the plurality of memory elements includes use of a reference memory element that does not receive data programming.

15. The method of claim 10, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states includes use of a reference memory element that does not receive data programming.

16. The method of claim 10, wherein utilizing at least one integrated circuit includes utilizing the plurality of re-programmable non-volatile memory elements that are individually switchable between more than two stable electrically detectable states by application of an electrical stimuli in addition to the first and second electrical stimuli, and

causing the selected one or more of the plurality of memory elements to simultaneously change between their individual more than two stable electrically detectable states includes applying the electrical stimuli in addition to the first and second electrical stimuli.