Phased locked loop with multiple voltage controlled oscillators

• US 9,467,092 B1
• Filed: 11/16/2015
• Issued: 10/11/2016
• Est. Priority Date: 11/16/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dreps, Daniel M., Friend, David M., Kesselring, Grant P., Strom, James D.
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/941,884
• Time in Patent Office: 330 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A phased locked loop (PLL) incorporates multiple voltage controlled oscillators including one that operates in a lower frequency range than an operational VCO used by the PLL. A VCO selection circuit allows the system to select from one or more alternate VCOs. A ring oscillator VCO may be used as the alternate VCO for a PLL that uses a LC VCO for the operational VCO. While the ring oscillator VCO provides lower performance, the ring oscillator VCO allows the system with the PLL to be run at a lower speed for testing, debugging or characterization.

Claims

1. An electronic circuit comprising:

a phased locked loop with a plurality of voltage controlled oscillators that each provides a variable high frequency signal required for the phased locked loop;

a first voltage controlled oscillator of the plurality of voltage controlled oscillators;

a second voltage controlled oscillator of the plurality of voltage controlled oscillators that is of a different type than the first voltage controlled oscillator and provides a frequency lower than the first voltage controlled oscillator with a greater frequency range than the first voltage controlled oscillator;

a multiplexor that inputs an output from each of the first and second voltage controlled oscillators and provides an output frequency for the phased locked loop; and

select logic connected to the multiplexor that selects whether the multiplexor uses the output from the first voltage controlled oscillator or the output from the second voltage controlled oscillator for the phased locked loop.

2. The electronic circuit of claim 1 wherein the first voltage controlled oscillator is an inductor/capacitor (LC) voltage controlled oscillator.

3. The electronic circuit of claim 1 wherein the second voltage controlled oscillator is a high frequency ring voltage controlled oscillator.

4. The electronic circuit of claim 1 wherein the high frequency ring voltage controlled oscillator comprises a four stage ring oscillator with a selectable frequency.

5. The electronic circuit of claim 1 wherein the first voltage controlled oscillator is used in normal operation of the PLL and the second voltage controlled oscillator is used for testing and debugging.

6. The electronic circuit of claim 5 wherein the first voltage controlled oscillator used in normal operation operates at about 30 GHz and the second voltage controlled oscillator used for testing and debugging operates between about 9 and 30 GHz.

7. The electronic circuit of claim 1 wherein the second voltage controlled oscillator has greater jitter characteristics than is acceptable during normal operation of the electronic circuit but is acceptable for testing and debugging.

8. An electronic circuit comprising:

a core for an integrated circuit that includes a high speed circuit for outputting a signal;

a phased locked loop in the high speed circuit having a plurality of voltage controlled oscillators that can each provide a variable high frequency signal required for the phased locked loop, the phased locked loop comprising;

a first voltage controlled oscillator of the plurality of voltage controlled oscillators;

a second voltage controlled oscillator of the plurality of voltage controlled oscillators that is of a different type than the first voltage controlled oscillator and provides a frequency lower than the first voltage controlled oscillator with a greater frequency range than the first voltage controlled oscillator;

a multiplexor that inputs an output from each of the first and second voltage controlled oscillators and provides an output frequency for the phased locked loop; and

select logic connected to the multiplexor that selects whether the multiplexor uses the output from the first voltage controlled oscillator or the output from the second voltage controlled oscillator for the phased locked loop; and

a clock divider that inputs a signal from the output of the multiplexor to use as a system clock for the integrated circuit.

9. The electronic circuit of claim 8 wherein the first voltage controlled oscillator is an inductor/capacitor (LC) voltage controlled oscillator.

10. The electronic circuit of claim 8 wherein the second voltage controlled oscillator is a high frequency ring voltage controlled oscillator.

11. The electronic circuit of claim 8 wherein the high frequency ring voltage controlled oscillator comprises a four stage ring oscillator with a selectable frequency.

12. The electronic circuit of claim 8 wherein the first voltage controlled oscillator is used in normal operation of the PLL and the second voltage controlled oscillator is used for testing and debugging.

13. The electronic circuit of claim 12 wherein the first voltage controlled oscillator used in normal operation operates at about 30 GHz and the second voltage controlled oscillator used for testing and debugging operates between about 9 and 30 GHz.

14. The electronic circuit of claim 8 wherein the second voltage controlled oscillator has greater jitter characteristics than is acceptable during normal operation of the electronic circuit but is acceptable for testing and debugging.

15. An electronic circuit comprising:

a processor core for an integrated circuit that includes a high speed serializer/deserializer for outputting a signal;

a phased locked loop in the serializer/deserializer having a plurality of voltage controlled oscillators that can each provide a variable high frequency signal required for the phased locked loop, the phased locked loop comprising;

a first inductor/capacitor (LC) voltage controlled oscillator;

a first high frequency ring voltage controlled oscillator that provides a greater frequency range than the first inductor/capacitor voltage controlled oscillator;

a multiplexor that inputs an output from the inductor/capacitor voltage controlled oscillator and an output from the first high frequency ring voltage controlled oscillator to provide an output frequency for the phased locked loop;

select logic connected to the multiplexor that selects whether the multiplexor uses the output from the first inductor/capacitor (LC) voltage controlled oscillator or the output from the first high frequency ring voltage controlled oscillator for the phased locked loop; and

a clock divider that inputs a signal from the output of the multiplexor to use as a system clock for the processor core.

16. The electronic circuit of claim 15 wherein the first high frequency ring voltage controlled oscillator comprises a four stage ring oscillator with a selectable frequency.

17. The electronic circuit of claim 15 wherein the first inductor/capacitor (LC) voltage controlled oscillator is used in normal operation of the PLL and the first high frequency ring voltage controlled oscillator is used for testing and debugging.

18. The electronic circuit of claim 17 wherein the first inductor/capacitor (LC) voltage controlled oscillator used in normal operation operates at about 30 GHz and the first high frequency ring voltage controlled oscillator used for testing and debugging operates between about 9 and 30 GHz.

19. The electronic circuit of claim 15 wherein the first high frequency ring voltage controlled oscillator has greater jitter characteristics than is acceptable during normal operation of the electronic circuit but is acceptable for margin testing and debugging.

20. The electronic circuit of claim 15 further comprising a second inductor/capacitor (LC) voltage controlled oscillator used in normal operation operates at about 16 GHz and a second high frequency ring voltage controlled oscillator operates in about the 9 to 16 GHz range, wherein the first inductor/capacitor (LC) voltage controlled oscillator used in normal operation operates at about 30 GHz and the first high frequency ring voltage controlled oscillator used for testing and debugging operates between about 16 to 30 GHz.