Low power and integrable on-chip architecture for low frequency PLL

• US 9,467,154 B2
• Filed: 01/12/2015
• Issued: 10/11/2016
• Est. Priority Date: 01/12/2015
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Saxena, Himanshu
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/594,447
• Publication Number:
  US 20160204785A1
• Time in Patent Office: 638 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

An integrated circuit including a phase detector; a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current; and a dual input loop filter coupled to the first charge pump and the second charge pump.

Claims

1. An integrated circuit, comprising:

a phase detector;

a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current, wherein the first charge pump and the second charge pump have synchronized outputs with respect to the inputs received from the phase detector; and

a dual input loop filter coupled to the first charge pump and the second charge pump and comprising a first input receiving the low current and a second input receiving the high current and an output providing for an output voltage.

2. An integrated circuit in accordance with claim 1, wherein the dual input loop filter includes a first capacitance coupled in parallel at a node with a series-coupled second capacitance and a resistor, the low current output of the first charge pump being coupled with the node and the high current output of the second charge pump being coupled between the second capacitance and the resistor.

3. An integrated circuit in accordance with claim 2, further comprising a common bias circuitry for charging the first charge pump and the second charge pump.

4. An integrated circuit in accordance with claim 1, further comprising a common bias circuitry for charging the first charge pump and second charge pump.

5. An integrated circuit in accordance with claim 3, wherein each of the first and second charge pumps is a current steering amplifier charge pump which can be implemented using low current.

6. An integrated circuit in accordance with claim 1, wherein the high current is K times the low current, wherein K is a predetermined value.

7. An integrated circuit in accordance with claim 2, wherein the second capacitance is approximately a tenth of an actual desired capacitance for stable negative feedback loop.

8. An integrated circuit in accordance with claim 3, further including a voltage control oscillator (VCO) coupled to the dual input loop filter.

9. An integrated circuit in accordance with claim 8, wherein the low frequency VCO includes a bias block capable of generating current in nA.

10. An integrated circuit in accordance with claim 9, wherein the bias block implements a source degeneration for do voltage to current transformation.

11. An integrated circuit in accordance with claim 10, wherein a resistor value for the source degeneration is scaled down by half factor.

12. An integrated circuit in accordance with claim 11, wherein a common mode voltage technique is used to scale down the value of the resistor.

13. An integrated circuit in accordance with claim 12, further comprising a current source branch which is a replica of existing bias circuitry.

19. An integrated circuit in accordance with claim 1, further comprising a voltage controlled oscillator receiving said output voltage.

20. An integrated circuit in accordance with claim 19, further comprising

a lock detector configured to continuously monitor an output of the phase locked loop circuit, wherein the lock detector is configured to generate a lock signal depending upon phase error between a reference clock and a feedback clock signal.

14. A phase locked loop circuit, comprising:

a phase detector;

a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current, wherein the first charge pump and the second charge pump have synchronized outputs with respect to the inputs received from the phase detector;

a dual input loop filter coupled to the first charge pump and the second charge pump and comprising a first input receiving the low current and a second input receiving the high current and an output providing for an output voltage; and

;

a lock detector configured to continuously monitor an output of the phase locked loop circuit.

15. A phase locked loop circuit in accordance with claim 14, the lock detector configured to generate a lock signal depending upon phase error between a reference clock and a feedback clock signal.

16. A phase locked loop circuit in accordance with claim 15, the lock detector having a delay cell to predefine a lock/unlock window for the lock signal.

17. A phase locked loop circuit in accordance with claim 16, wherein the delay cell includes a bias circuit and delay cell replica of an associated VCO, such that a change in VCO frequency will be replicated in the delay cell of the lock detector circuit.

18. An integrated circuit, comprising:

a phase detector;

a first capacitor coupled in series with a resistor between a first node and ground;

a second capacitor coupled between the first node and ground;

a first charge pump coupled with the phase detector and configured to receive inputs from the phase detector and generating a first current which is fed to a second node between the first capacitor and the resistor, wherein the first charge pump and the second charge pump have synchronized outputs with respect to the inputs received from the phase detector;

a second charge pump coupled with the phase detector and configured to receive inputs from the phase detector and generating a second current which is fed to the first node, wherein the first current is higher than the second current; and

wherein an output voltage is available at the first node.