Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
First Claim
1. A processor comprising:
- a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and
one or more execution units, responsive to the decoded first instruction, to;
perform one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set if a first indicator of said one or more substitution function indicators indicates a first substitution function;
perform one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set if a second indicator of said one or more substitution function indicators indicates a second substitution function; and
store a result of the first instruction in a SIMD destination register.
1 Assignment
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Accused Products
Abstract
Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.
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Citations
37 Claims
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1. A processor comprising:
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a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and one or more execution units, responsive to the decoded first instruction, to; perform one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set if a first indicator of said one or more substitution function indicators indicates a first substitution function; perform one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set if a second indicator of said one or more substitution function indicators indicates a second substitution function; and store a result of the first instruction in a SIMD destination register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A machine-readable medium to record functional descriptive material having stored thereon one or more executable instructions including a first instruction, which if executed on behalf of a thread of a machine causes the machine to:
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access a first source data operand set of elements, a second source data operand set of elements, and one or more substitution function indicators; perform a first one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function; perform a first one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function; and store a set of result elements of the one or more SM4-round exchange and the one or more SM4 key generation in a SIMD register. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A method comprising:
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decoding a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and responsive to the first instruction, accessing the first source data operand set, accessing the second source data operand set, performing a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function, performing the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and storing a set of result elements of the first instruction in a SIMD destination register. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A processing system comprising:
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a memory to store a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation; and a processor comprising; an instruction fetch stage to fetch the first instruction; a decode stage to decode a first instruction, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and one or more execution units, responsive to the decoded first instruction, to; access the first source data operand set, access the second source data operand set, perform a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function, perform the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A apparatus in a processor comprising:
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a memory to store a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and a processor comprising; one or more encryption units, responsive to the first instruction, to; perform a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function, perform the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register. - View Dependent Claims (35, 36, 37)
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Specification