Timing channel circuitry for creating pulses in an implantable stimulator device

• US 9,468,771 B2
• Filed: 09/18/2015
• Issued: 10/18/2016
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Griffith, Paul J., Marnfeldt, Goran N., Parramon, Jordi
• Primary Examiner(s): Holmes, Rex R
• Application Number:
  US14/858,554
• Publication Number:
  US 20160008611A1
• Time in Patent Office: 396 Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware

Abstract

Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Claims

1. An implantable stimulator device, comprising:

a memory for storing pulse parameters defining a plurality of pulse phases for a periodic pulse, wherein the pulse parameters for each of the plurality of pulse phases are stored in at least one address in the memory,

control circuitry for receiving first data from the at least one address in the memory for each of the pulse phases, wherein the first data is indicative of the number of the at least one address in the memory for each of the pulse phases; and

stimulation circuitry for receiving second data from the at least one address in the memory for each of the pulse phases, wherein the second data configures the stimulation circuitry to form the pulse phases at electrodes for stimulating a patient'"'"'s tissue,

wherein the plurality of pulse phases do not comprise the same number of addresses in the memory.

2. The implantable stimulator device of claim 1, wherein the second data comprises amplitude data, active electrode, and electrode polarity data for at least some of the plurality of pulse phases.

3. The implantable stimulator device of claim 1, wherein the plurality of pulse phases are selected from the group consisting of an active phase that actively provides current at the electrodes, a recovery phase for collecting stored charge but which does not actively provide current at the electrodes, and a quite phase that does not actively provide current at the electrodes.

4. The implantable stimulator device of claim 3, wherein the active phase, the recovery phase, and the quite phase are stored in different numbers of addresses in the memory.

5. The implantable stimulator device of claim 1, wherein the control circuitry uses the first data indicative of the number of the at least one address in the memory for each of the pulse phases to provide addresses to the memory for providing the second data for each pulse phase to the stimulation circuitry.

6. An implantable stimulator device, comprising:

a memory for storing pulse parameters for a pulse phase comprising a plurality of sequential sub-phases, wherein the pulse phase has an amplitude that is not constant, wherein the pulse phase has a first duration,

wherein data for each sub-phase of the non-constant amplitude pulse phase is stored in a range of addresses in the memory,

wherein each range of addresses comprises at least an amplitude of the sub-phase and a second duration of the sub-phase less than the first duration, wherein the amplitudes in the ranges of addresses are not all equal; and

stimulation circuitry for sequentially receiving the data for each sequential sub-phase from each of the ranges of addresses to configure the stimulation circuitry to form the non-constant amplitude pulse phase at electrodes for stimulating a patient'"'"'s tissue,

wherein the data for each sub-phase comprises the same number of addresses in the memory.

7. The implantable stimulator device of claim 6, wherein the data for each sub-phase further comprises active electrode and electrode polarity data for each sub-phase.