Test instrument having a configurable interface

• US 9,470,759 B2
• Filed: 10/28/2011
• Issued: 10/18/2016
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Bourassa, Stephen J., McGoldrick, Michael Francis, Kaushansky, David, Fluet, Michael Thomas
• Primary Examiner(s): Toatley, Gregory J
• Assistant Examiner(s): Ishizuka, Yoshihisa
• Application Number:
  US13/284,378
• Publication Number:
  US 20130110446A1
• Time in Patent Office: 1,817 Days
• Field of Search: 702/122
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

In general, a test instrument includes a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system including multiple processing devices, and a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface including physical ports, to which different configurations are assignable.

Claims

1. A test instrument comprising:

a processing system programmed to control operation of the test instrument, including communication with a control system, and programmed to run one or more test programs to test a device interfaced to the test instrument, the processing system comprising multiple processing devices, the processing system comprising a first processing system and a second processing system, with the second processing system being between the device interfaced to the test instrument and the first processing system; and

programmable logic between the second processing system and the device interfaced to the test instrument, the programmable logic comprising a configurable interface, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface comprising physical ports, to which different configurations are assignable based on whether the first processing system or the second processing system is executing a test program to test the device interfaced to the test instrument, the different configurations being assignable in real-time during execution of the test program;

wherein the first processing system, the second processing system, and the programmable logic are each configured to perform testing on the device interfaced to the test instrument, with the second processing system having less test latency than the first processing system, and the programmable logic having less test latency than the first processing system and the second processing system.

2. The test instrument of claim 1, wherein the programmable logic is programmable through application of a load to the programmable logic, the load providing functionality that enables the physical ports to assume the different configurations.

3. The test instrument of claim 2, wherein the programmable logic comprises a field programmable gate array (FPGA);

and

wherein the load is a single load that enables the physical ports to assume the different configurations in response to control inputs.

4. The test instrument of claim 3, wherein the single load further configures the FPGA to perform one or more tests on the device interfaced to the test instrument.

5. The test instrument of claim 3, wherein the processing system is programmed to provide the control inputs to the FPGA.

6. The test instrument of claim 1, wherein the different configurations relate to functions of the ports, including whether ports operate as inputs or outputs.

7. The test instrument of claim 1, wherein the different configurations relate to widths of the ports.

8. The test instrument of claim 1, wherein the different configurations relate to frequencies of signals transmitted through the ports.

9. The test instrument of claim 1, wherein the different configurations relate to memory depth associated with the ports.

10. The test instrument of claim 1, wherein the first processing system is programmable to run one or more test programs to test the device interfaced to the test instrument, and is programmed to control operation of the test instrument;

and

wherein the second processing system is dedicated to device testing, the second processing system comprising multiple processing devices that are programmable to run one or more test programs to test the device interfaced to the test instrument.

11. A method comprising:

configuring a processing system comprised of multiple processing devices to control operation of a test instrument, including communication with a control system, the configuring comprising programming the processing system to run one or more test programs to test a device interfaced to the test instrument, the processing system comprising a first processing system and a second processing system, with the second processing system being between the first processing system and the device interfaced to the test instrument; and

configuring a configurable interface implemented in programmable hardware, through which communications are exchanged with the device interfaced to the test instrument, the configurable interface comprising physical ports, to which different configurations are assignable based on whether the first processing system or the second processing system is executing a test program to test the device interfaced to the test instrument, the different configurations being assignable in real-time during execution of the test program;

wherein the first processing system, the second processing system, and the programmable hardware are each configured to perform testing on the device interfaced to the test instrument, with the second processing system having less test latency than the first processing system, and the programmable hardware having less test latency than the first processing system and the second processing system.

12. The method of claim 11, wherein the configurable interface comprises programmable logic, the programmable logic being programmable through application of a load to the logic, the load providing functionality that enables the physical ports to assume the different configurations.

13. The method of claim 12, wherein the programmable logic comprises a field programmable gate array (FPGA);

and

wherein the load is a single load that enables the physical ports to assume the different configurations in response to control inputs.

14. The method of claim 13, wherein the single load further configures the FPGA to perform one or more tests on the device interfaced to the test instrument.

15. The method of claim 11, wherein the different configurations relate to functions of the ports, including whether ports operate as inputs or outputs.

16. The method of claim 11, wherein the different configurations relate to widths of the ports.

17. The method of claim 11, wherein the different configurations relate to frequencies of signals transmitted through the ports.

18. The method of claim 11, wherein the different configurations relate to memory depth associated with the ports.

19. The method of claim 11, wherein the first processing system is programmable to run one or more test programs to test the device interfaced to the test instrument, and is programmed to control operation of the test instrument;

and

wherein the second processing system is dedicated to device testing, the second processing system comprising multiple processing devices that are programmable to run one or more test programs to test the device interfaced to the test instrument.