Restricting clock signal delivery in a processor

• US 9,471,088 B2
• Filed: 06/25/2013
• Issued: 10/18/2016
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gendler, Alexander, Rotem, Efraim, Mandelblat, Julius, Lyakhov, Alexander, Novakovsky, Larisa, Leifman, George, Makovsky, Lev, Sabba, Ariel, Tokman, Niv
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ERDMAN, CHAD G
• Application Number:
  US13/925,986
• Publication Number:
  US 20140380081A1
• Time in Patent Office: 1,211 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a power controller to perform power management for the processor, the power controller to generate a restriction command responsive to a determination that at least one core of the processor is in operation within a threshold of a processor constraint and send the restriction command to the at least one core; and

the at least one core to execute instructions, the at least one core including a plurality of units and a clock generation logic to receive and distribute a first clock signal to the plurality of units of the at least one core, a restriction logic to receive the restriction command and responsive to the restriction command to dynamically cause the clock generation logic to reduce delivery of the first clock signal to at least one of the plurality of units while the first clock signal is delivered to at least one other of the plurality of units of the at least one core without restriction, wherein the reduced delivery of the first clock signal is at a lower frequency than a frequency of the first clock signal, the at least one core further including a clock crossing logic to couple the at least one core to a system agent logic of the processor, wherein the clock crossing logic is to operate at the first clock signal without restriction, and a buffer coupled to the clock crossing logic, the buffer to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction.

2. The processor of claim 1, wherein the clock generation logic is to prevent a first number of cycles of the first clock signal from being distributed to the plurality of units for each cycle of the first clock signal distributed to the plurality of units.

3. The processor of claim 1, wherein the plurality of units includes a first subset of units to receive the first clock signal with the reduced delivery and a second subset of units to receive the first clock signal without restriction.

4. The processor of claim 1, further comprising:

a bypass path coupled between a first unit of the plurality of units and the clock crossing logic; and

a second path coupled between the first unit and the buffer, wherein the bypass path is to be blocked responsive to the restriction command.

5. The processor of claim 1, further comprising:

a first counter to count cycles of the first clock signal without restriction; and

a second counter to count cycles of the first clock signal with the reduced delivery.

6. The processor of claim 1, wherein the restriction command is received from the power controller of the processor responsive to detection of a thermal event of the processor, wherein the clock generation logic is to perform the reduced delivery of the first clock signal without stopping the at least one core.

7. The processor of claim 1, wherein the restriction command is received from the power controller of the processor responsive to a low power state exit request for a second core, wherein the clock generation logic is to perform the reduced delivery of the first clock signal without stopping the at least one core, the first clock signal at a turbo mode frequency.

8. The processor of claim 7, wherein the second core is to begin the low power state exit concurrently with the reduced delivery of the first clock signal.

9. A non-transitory storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving a clock signal in a clock generation circuit of a core of a processor;

receiving a clock restriction command in clock restriction logic of the core from a power controller of the processor;

determining a restriction level based on the clock restriction command, the clock restriction command including a data portion having a value to indicate the restriction level;

controlling the clock generation circuit according to the restriction level to drive a restricted clock signal to at least one functional unit of the core, wherein the restricted clock signal includes a reduced number of cycles of the clock signal;

controlling a clock crossing logic of the core to operate at the first clock signal without restriction, and

controlling a buffer coupled to the clock crossing logic to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction.

10. The non-transitory storage medium of claim 9, wherein the method further comprises operating the core with the clock signal without restriction and thereafter operating the core with the restricted clock signal, without stopping the core.

11. The non-transitory storage medium of claim 9, wherein the method further comprises receiving the clock restriction command when the core is operating within at least a threshold of at least one processor constraint.

12. The non-transitory storage medium of claim 11, wherein the method further comprises determining whether the core is operating within the at least one threshold, including comparing at least one power consumption metric to the at least one threshold.

13. The non-transitory storage medium of claim 9, wherein the method further comprises receiving the clock restriction command responsive to a low power state exit request for a second core, and controlling the clock generation circuit to drive the restricted clock signal concurrently with the second core exit from the low power state.

14. A system comprising:

a multicore processor including a plurality of cores, each core including a clock generator to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a clock restriction command and to cause reduced delivery of the first clock signal to at least one of the plurality of units without execution of a frequency change protocol while at least one other of the plurality of units is to receive the first clock signal without restriction, a power controller coupled to the plurality of cores to issue the clock restriction command to at least one core of the processor responsive to a determination that the at least one core of the processor is in operation within a threshold of a processor constraint, and a clock logic to provide the first clock signal to at least one of the plurality of cores, wherein a first core comprises;

a clock crossing logic to couple the first core to another portion of the processor, the first core and the other portion to operate at different frequencies; and

a buffer coupled to the clock crossing logic, the buffer to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

15. The system of claim 14, wherein the first core further comprises:

a bypass path coupled between a first unit of the plurality of units and the clock crossing logic; and

a second path coupled between the first unit and the buffer, wherein the bypass path is to be blocked responsive to the clock restriction command.

16. The system of claim 15, further comprising a second core,

wherein the power controller is to send the clock restriction command to the first core responsive to a low power state exit request for the second core, and the clock generator logic is to perform the reduced delivery of the first clock signal responsive to the clock restriction command concurrently with the second core low power state exit.