Microprocessor based power management system architecture

• US 9,471,121 B2
• Filed: 11/14/2012
• Issued: 10/18/2016
• Est. Priority Date: 11/14/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bonnett, William B, Saha, Arindam, Dham, Ish Kumar, Sarathy, Vijay
• Primary Examiner(s): Nguyen, Phil
• Application Number:
  US13/676,573
• Publication Number:
  US 20130124895A1
• Time in Patent Office: 1,434 Days
• Field of Search: 713/323, 713/300
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

Claims

1. An electronic device disposed on a single integrated circuit comprising:

a plurality of power domains operable to be independently powered, said plurality of power domains including at least one microprocessor domain including a programmable main microprocessor;

a power control manager connected to said plurality of power domains for selectively powering said plurality of power domains, said power control manager including

a set of control registers storing individual control bits,

a power switch for each power domain connected to a corresponding control register, each power switch having an ON state supplying electric power to said corresponding power domain upon a first state of said corresponding control register and an OFF state not supplying electric power to said corresponding power domain upon a second state of said corresponding control register opposite to said first state, and

a programmable power management microprocessor separate from said programmable main microprocessor including a central processing unit and a memory storing an alterable set of program instructions to control said state of individual control bits of said set of control registers, said programmable power management microprocessor having a smaller data computational capacity than said main microprocessor, wherein the alterable set of program instructions is dynamically alterable at an application level after manufacture of said single integrated circuit by introduction of new states and sequences into said memory.

2. The electronic device of claim 1, wherein:

said plurality of power domains includes a peripheral domain including at least one data communications peripheral controlling communication between said programmable main microprocessor and external devices.

3. The electronic device of claim 1, wherein:

said plurality of power domains includes a peripheral domain including a memory controller adapted for connection to an external memory external to said electronic device controlling communication between said programmable main microprocessor and the external memory.

4. The electronic device of claim 1 wherein:

said programmable power management microprocessor is programmable to select one of a set of reduced power modes, each reduced power mode selectively powering a unique subset of said plurality of power domains.

5. The electronic device of claim 1, further comprising:

a plurality of clock domains operable to be independently clocked;

said power control manager wherein said set of control registers includes a bit corresponding to each clock domain, and said programmable power management microprocessor operable to control said state of individual control bits of said set of control register corresponding to said clock domain to controllably supply a clock to said clock domain or block supply of said clock to said clock domain.

6. The electronic device of claim 5, wherein:

said programmable power management microprocessor is programmable to select one of a set of reduced power modes, each reduced power mode selectively powering a unique subset of said plurality of power domains and selectively supplying clocks to a unique subset of said clock domains.

7. The electronic device of claim 1, further comprising:

a power supply generation integrated circuit separate from said single integrated circuit supplying a plurality of electrical voltages to said single integrated circuit.

8. The electronic device of claim 7, wherein:

said power control manager is connected to said power supply generation integrated circuit and controls a voltage level of at least one of said plurality of electrical voltages.

9. The electronic device of claim 8, wherein:

said single integrated circuit further includes an independently powered real time clock generating a wakeup signal upon reaching a predetermined real time; and

said power supply generation integrated circuit is connected to said real time clock and generates a predetermined set of voltage levels on said plurality of electrical voltages upon detection of said wakeup signal.

10. The electronic device of claim 9, further comprising:

a plurality of clock domains operable to be independently clocked;

said power control manager wherein said set of control registers includes a bit corresponding to each clock domain, and said programmable power management microprocessor operable to control said state of individual control bits of said set of control register corresponding to said clock domain to controllably supply a clock to said clock domain or block supply of said clock to said clock domain; and

wherein said real time clock includes a clock oscillator independent of said power control manager controllably supplied clocks.

11. The electronic device of claim 1, wherein:

said programmable power management microprocessor employs data words having a first size, said programmable main microprocessor employs data words having a second size, said first size smaller than second size.

12. The electronic device of claim 1, wherein said programmable power management microprocessor employs data a first clock frequency, said programmable main microprocessor employs a second clock frequency, said first clock frequency less than second clock frequency.