Techniques for putting platform subsystems into a lower power state in parallel

• US 9,471,132 B2
• Filed: 09/27/2013
• Issued: 10/18/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bibikar, Vasudev, Mavila, Rajith K.
• Primary Examiner(s): LEE, THOMAS C
• Assistant Examiner(s): DeRose, Volvick
• Application Number:
  US14/040,156
• Publication Number:
  US 20150095677A1
• Time in Patent Office: 1,117 Days
• Field of Search: 713/323
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.

Claims

1. An apparatus, comprising:

processor circuitry; and

a power management component for execution on the processor circuitry, the power management component to;

determine a sleep configuration state for each of a plurality of subsystems of a device having an associated subsystem sleep control register for entry into a lower power state,

configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems,

enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state, and

write a control bit for each of a plurality of power control registers in a power management power control register to configure each of the plurality of power control registers in a particular order, wherein each of the plurality of subsystems is associated with a one of the plurality of power control registers and wherein the particular order is based on the order in which the control bits are written.

2. The apparatus of claim 1, the power management component to determine which of the plurality of subsystems to disable and which of the subsystems to keep enabled when the device is in the lower power state based on the sleep configuration state in the associated subsystem sleep control register.

3. The apparatus of claim 1, the plurality of power control registers comprising at least one of a firewall enable power control register, a power enable power control register, a clock enable power control register and a reset power control register.

4. The apparatus of claim 1, the power management component to configure a same register type of the plurality of power control registers for each of the subsystems in parallel by writing a control bit for each of the plurality of power control registers in a power management power control register.

5. The apparatus of claim 1, the power management component to determine a wake configuration state for each of the plurality of subsystems having an associated subsystem wake control register for exiting a lower power state, configure each of the associated subsystem wake control registers with the wake configuration state for each of the subsystems and enable the wake configuration state for each of the subsystems in parallel when transitioning from the lower power state.

6. The apparatus of claim 5, wherein each of the subsystems is associated with one or more power control registers and the power management component to configure each of the one or more power control registers when transitioning from the lower power state is based on the wake configuration state.

7. An article comprising a non-transitory computer-readable storage medium containing a plurality of instructions that when executed enable a processor circuit to:

determine a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state;

configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems;

enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state; and

,

write a control bit for each of a plurality of power control registers in a power management power control register to configure each of the plurality of power control registers in a particular order, wherein each of the plurality of subsystems is associated with a one of the plurality of power control registers and wherein the particular order is based on the order in which the control bits are written.

8. The article of claim 7, comprising the non-transitory computer-readable storage medium containing the plurality of instruction that when executed enable the processor circuit to determine which of the plurality of subsystems to disable and which of the subsystems to keep enabled based on the sleep configuration state in the associated subsystem sleep control register.

9. The article of claim 7, the plurality of power control registers comprising at least one of a firewall enable power control register, a power enable power control register, a clock enable power control register and a reset power control register.

10. The article of claim 7, comprising the non-transitory computer-readable storage medium containing the plurality of instruction that when executed enable the processor circuit to configure a same register type of the plurality of power control registers for each of the subsystems in parallel by writing a control bit for each of the plurality of power control registers in a power management power control register.

11. The article of claim 7, comprising the non-transitory computer-readable storage medium containing the plurality of instruction that when executed enable the processor circuit to:

determine a wake configuration state for each of the plurality of subsystems having an associated subsystem wake control register for exiting a lower power state;

configure each of the associated subsystem wake control registers with the wake configuration state for each of the subsystems; and

enable the wake configuration state for each of the subsystems in parallel when transitioning from the lower power state.

12. The article of claim 11, wherein each of the subsystems is associated with one or more power control registers and the article comprising the computer-readable storage medium containing the plurality of instruction that when executed enable the processor circuit to configure each of the one or more power control registers when transitioning from the lower power state is based on the wake configuration state.

13. An apparatus, comprising:

processing logic to determine a sleep configuration state for each of a plurality of subsystems of a device having an associated subsystem sleep control register for entry into a lower power state, configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems, enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state, and write a control bit for each of a plurality of power control registers in a power management power control register to configure each of the plurality of power control registers in a particular order, wherein each of the plurality of subsystems is associated with a one of the plurality of power control registers and wherein the particular order is based on the order in which the control bits are written.

14. The apparatus of claim 13, the processing logic to determine which of the plurality of subsystems to disable and which of the subsystems to keep enabled when the device is in the lower power state based on the sleep configuration state in the associated subsystem sleep control register.

15. The apparatus of claim 13, the plurality of power control registers comprising at least one of a firewall enable power control register, a power enable power control register, a clock enable power control register and a reset power control register.

16. The apparatus of claim 13, the processing logic to configure a same register type of the plurality of power control registers for each of the subsystems in parallel by writing a control bit for each of the plurality of power control registers in a power management power control register.

17. The apparatus of claim 13, the processing logic to determine a wake configuration state for each of the plurality of subsystems having an associated subsystem wake control register for exiting a lower power state, configure each of the associated subsystem wake control registers with the wake configuration state for each of the subsystems and enable the wake configuration state for each of the subsystems in parallel when transitioning from the lower power state.