Service processor patch mechanism

• US 9,471,133 B2
• Filed: 05/19/2014
• Issued: 10/18/2016
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): Elmore, Stephen
• Application Number:
  US14/281,758
• Publication Number:
  US 20150067263A1
• Time in Patent Office: 883 Days
• Field of Search: 711/130, 711/154, 711/156, 711/158, 712/227, 713/1, 713/2
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Claims

1. A microprocessor, comprising:

a plurality of processing cores;

a service processing unit; and

a memory accessible by both the service processing unit and the plurality of processing cores; and

wherein at least one of the plurality of processing cores is configured to write a patch to the memory, wherein the patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

2. The microprocessor of claim 1, wherein the plurality of processing cores have an instruction set architecture, wherein the service processing unit is not architecturally visible to execute instructions of the instruction set architecture of the plurality of processing cores, wherein the service processing unit performs operations used to debug the microprocessor.

3. The microprocessor of claim 1, further comprising:

a second memory, configured to hold instructions to be fetched from the second memory and executed by the service processing unit, wherein the second memory is a read-only memory.

4. The microprocessor of claim 3, further comprising:

a register, configured to store an address, wherein the register is writeable by the at least one of the plurality of processing cores; and

wherein the service processing unit is configured to fetch and execute its first instruction, after being reset, from one of the first and second memories at the address specified in the register.

5. The microprocessor of claim 1, wherein the memory is further configured to hold data read and written by microcode executed by all of the plurality of processing cores.

6. The microprocessor of claim 1, further comprising:

a cache memory, shared by the plurality of processing cores; and

wherein the service processing unit is configured to write to a control register to stop one or more of the plurality of processing cores from issuing requests to the shared cache memory.

7. The microprocessor of claim 1, further comprising:

a cache memory, shared by the plurality of processing cores; and

wherein the service processing unit is configured to write to a control register to stop the shared cache memory from acknowledging requests to the shared cache memory made by the plurality of processing cores.

8. The microprocessor of claim 1, further comprising:

a cache memory, shared by the plurality of processing cores; and

wherein the service processing unit is configured to write to a control register to resize the shared cache memory.

9. The microprocessor of claim 1, further comprising:

a bus interface, configured to interface the microprocessor with a system bus external to the microprocessor; and

wherein the service processing unit is configured to write to a control register to control the bus interface to perform transactions on the system bus.

10. The microprocessor of claim 1, further comprising:

a programmable interrupt controller, configured to control interrupt requests to the microprocessor; and

wherein the service processing unit is configured to write to a control register to control the programmable interrupt controller to emulate an input/output (I/O) device to the plurality of processing cores.

11. The microprocessor of claim 1,

wherein each of the plurality of processing cores comprises a plurality of functional units;

and

wherein the service processing unit is configured to write to a control register to configure a performance feature of one or more of the plurality of functional units of the plurality of processing cores, wherein the performance feature is one or more performance features from the following list;

a branch prediction algorithm and a data prefetch algorithm.

12. A method to be performed by a microprocessor having a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores, the method comprising:

writing, by at least one of the plurality of processing cores, a patch to the memory, wherein the patch comprises one or more instructions;

fetching from the memory, by the service processing unit, the one or more instructions of the patch after said writing the patch to the memory by the at least one of the plurality of processing cores; and

executing, by the service processing unit, the fetched instructions of the patch.

13. The method of claim 12, wherein the plurality of processing cores have an instruction set architecture, wherein the service processing unit is not architecturally visible to execute instructions of the instruction set architecture of the plurality of processing cores, wherein the service processing unit performs operations used to debug the microprocessor.

14. The method of claim 12, further comprising;

reading and writing data from and to, respectively, the memory, by microcode executed by each core of the plurality of processing cores.

15. The method of claim 12, further comprising:

writing, by the service processing unit, to a control register to stop one or more of the plurality of processing cores from issuing requests to a cache memory of the microprocessor that is shared by the plurality of processing cores.

16. The method of claim 12, further comprising:

writing, by the service processing unit, to write to a control register to stop a cache memory of the microprocessor that is shared by the plurality of processing cores from acknowledging requests to the shared cache memory made by the plurality of processing cores.

17. The method of claim 12, further comprising:

a cache memory, shared by the plurality of processing cores; and

writing, by the service processing unit, to a control register to resize a cache memory of the microprocessor that is shared by the plurality of processing cores.

18. The method of claim 12, wherein the microprocessor also includes a bus interface configured to interface the microprocessor with a system bus external to the microprocessor, the method further comprising:

writing, by the service processing unit, to write to a control register to control the bus interface to perform transactions on the system bus.

19. The method of claim 12, wherein the microprocessor also includes a programmable interrupt controller, configured to control interrupt requests to the microprocessor, the method further comprising:

writing, by the service processing unit, to write to a control register to control the programmable interrupt controller to control the programmable interrupt controller to emulate an input/output (I/O) device to the plurality of processing cores.

20. The method of claim 12, wherein each of the plurality of processing cores includes a plurality of functional units, the method further comprising:

writing, by the service processing unit, to a control register to configure a performance feature of one or more of the plurality of functional units of the plurality of processing cores, wherein the performance feature is one or more performance features from the following list;

a branch prediction algorithm and a data prefetch algorithm.

21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

first program code for specifying a plurality of processing cores;

second program code for specifying a service processing unit; and

third program code for specifying a memory accessible by both the service processing unit and the plurality of processing cores;

wherein at least one of the plurality of processing cores is configured to write a patch to the memory, wherein the patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.