Micro-coded transcendental instruction execution

• US 9,471,305 B2
• Filed: 08/12/2014
• Issued: 10/18/2016
• Est. Priority Date: 05/09/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Alsup, Mitchell
• Primary Examiner(s): Richer, Joni
• Application Number:
  US14/458,145
• Publication Number:
  US 20150324949A1
• Time in Patent Office: 798 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/03 working, at least partly, by table look-up G06F1/025 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 3/4007 based on interpolation, e.g. bilinear interpolation image demosaicing G06T3/4015; edge-driven or edge-based scaling G06T3/403

Abstract

A method for graphics processing includes generating one or more transcendental instructions in a graphics processing unit (GPU). Micro-code is formed for processing the one or more transcendental instructions in the GPU. The micro-code is processed using an iterative process including cubic interpolation and an evaluation of a cubic polynomial.

Claims

1. A method for graphics processing comprising:

obtaining at least one transcendental instruction in a graphics processing unit (GPU);

forming micro-code for processing the at least one transcendental instruction in a shader data path in the GPU, wherein the micro-code supplies a clock cycle number; and

processing the micro-code based on the clock cycle number and an index to a first table using an iterative process including cubic interpolation and an evaluation of a cubic polynomial.

2. The method of claim 1, wherein the iterative process comprises performing an argument reduction pass and multiple evaluation passes, and the multiple evaluation passes determines results of polynomials.

3. The method of claim 2, wherein the multiple evaluation passes comprise multiple Horner evaluation passes.

4. The method of claim 3, wherein the at least one transcendental instruction is processed using a floating point multiplier and addition unit (FMAD) configured for processing the at least one transcendental instruction using the first table, a second table, a first store device, and a second store device.

5. The method of claim 4, wherein the first table contains coefficients for the multiple Horner evaluation passes, a first portion of the first table is accessed in a first Horner evaluation pass, a second portion of the first table is accessed in a second Horner evaluation pass, and a third portion of the first table is accessed in a third Horner evaluation pass.

6. The method of claim 5, wherein the second table is accessed during a last clock cycle of a first pass of an instruction, and a coefficient of the second table is available at a start of the first Horner evaluation pass.

7. The method of claim 6, wherein the first store device is used to hold a table indexing function, and the second store device is used to hold a reduced argument, and the reduced argument is used during each of the three Horner evaluation passes.

8. The method of claim 7, wherein the at least one transcendental instruction comprises:

reciprocal, reciprocal square root, square root, sin, cos, ln 2(x), ln(x), log(x), 2**x, e**x, and 10**x determinations.

9. The method of claim 8, wherein a particular set of coefficients from the first table and the second table are selected based on the at least one transcendental instruction and on an argument to the at least one transcendental instruction, and the particular set of coefficients are used during the three Horner evaluation passes.

10. The method of claim 1, wherein:

the GPU is used by an electronic device;

the micro-code comprises a sequence of micro-coded instructions; and

the processing of the micro-code comprises;

switching an instruction pipeline of the GPU from a first mode to a second mode, the second mode providing control of the instruction pipeline for iterative processing of the micro-code; and

in response to processing the micro-code, switching the instruction pipeline to the first mode for pipelined processing of the instruction pipeline.

11. The method of claim 10, wherein:

the electronic device comprises a mobile electronic device; and

the processing of the micro-code further comprises;

responsive to the switching of the instruction pipeline to the second mode;

freezing a first counter of the instruction pipeline; and

incrementing a second counter of the instruction pipeline; and

responsive to the switching the instruction pipeline to the first mode;

incrementing the first counter.

12. A non-transitory computer-readable medium having instructions which when executed on a computer perform a method comprising:

obtaining at least one transcendental instruction in a graphics processing unit (GPU);

forming micro-code for processing the at least one transcendental instruction in a shader data path in the GPU, wherein the micro-code supplies a clock cycle number; and

processing the micro-code based on the cycle number and an index to a first table using an iterative process including cubic interpolation and an evaluation of a cubic polynomial.

13. The medium of claim 12, wherein the iterative process comprises performing an argument reduction pass and multiple evaluation passes, and the multiple evaluation passes determines results of polynomials.

14. The medium of claim 13, wherein the multiple evaluation passes comprise multiple Horner evaluation passes.

15. The medium of claim 14, wherein the at least one transcendental instruction is processed using a floating point multiplier and addition unit (FMAD) configured for processing the at least one transcendental instruction using the first table, a second table, a first store device, and a second store device.

16. The medium of claim 15, wherein the first table contains coefficients for the multiple Horner evaluation passes, a first portion of the first table is accessed in a first Horner evaluation pass, a second portion of the first table is accessed in a second Horner evaluation pass, and a third portion of the first table is accessed in a third Horner evaluation pass.

17. The medium of claim 16, wherein:

the second table is accessed during a last clock cycle of a first pass of an instruction;

a coefficient of the second table is available at a start of the first Horner evaluation pass;

the first store device is used to hold a table indexing function;

the second store device is used to hold a reduced argument; and

the reduced argument is used during each of the three Horner evaluation passes.

18. The medium of claim 17, wherein the at least one transcendental instruction comprises:

reciprocal, reciprocal square root, square root, sin, cos, ln 2(x), ln(x), log(x), 2**x, e**x, and 10**x determinations, a particular set of coefficients from the first table and the second table are selected based on the at least one transcendental instruction and on an argument to the at least one transcendental instruction, and the particular set of coefficients are used during the three Horner evaluation passes.

19. The medium of claim 12, wherein:

the GPU uses a single-instruction multiple-thread (SIMT) processing architecture;

the GPU is employed by an electronic device;

the micro-code comprises a sequence of micro-coded instructions; and

the processing of the micro-code comprises;

switching an instruction pipeline of the GPU from a first mode to a second mode, the second mode providing control of the instruction pipeline for iterative processing of the micro-code; and

in response to processing the micro-code, switching the instruction pipeline to the first mode for pipelined processing of the instruction pipeline.

20. A graphics processing unit (GPU) for an electronic device comprising:

at least one processing element coupled to a memory device, wherein the at least one processing element is configured to;

obtain at least one transcendental instruction in the GPU, form micro-code to process the at least one transcendental instruction in a shader data path in the GPU, wherein the micro-code supplies a clock cycle number, and process the micro-code based on the clock cycle number and an index to a first table using an iterative process including cubic interpolation and an evaluation of a cubic polynomial.

21. The GPU of claim 20, wherein the iterative process is configured to perform an argument reduction pass and multiple evaluation passes, and the multiple evaluation passes are configured to determine results of polynomials.

22. The GPU of claim 21, wherein the multiple evaluation passes comprise multiple Horner evaluation passes.

23. The GPU of claim 22, wherein the at least one transcendental instruction is processed using a floating point multiplier and addition unit (FMAD) configured to process the at least one transcendental instructions using the first table, a second table, a first store device, and a second store device.

24. The GPU of claim 23, wherein the first table contains coefficients for the multiple Horner evaluation passes, a first portion of the first table is accessed in a first Horner evaluation pass, a second portion of the first table is accessed in a second Horner evaluation pass, and a third portion of the first table is accessed in a third Horner evaluation pass.

25. The GPU of claim 24, wherein:

the second table is accessed during a last clock cycle of a first pass of an instruction;

a coefficient of the second table is available at a start of the first Horner evaluation pass;

the first store device is configured to hold a table indexing function;

the second store device is configured to hold a reduced argument; and

the reduced argument is used during each of the three Horner evaluation passes.

26. The GPU of claim 25, wherein the at least one transcendental instruction comprises:

reciprocal, reciprocal square root, square root, sin, cos, ln 2(x), ln(x), log(x), 2**x, e**x, and 10**x determinations.

27. The GPU of claim 26, wherein a particular set of coefficients from the first table and the second table are selected based on the at least one transcendental instruction and on an argument to the at least one transcendental instruction, and the particular set of coefficients are used during the three Horner evaluation passes.

28. The GPU of claim 21, wherein the GPU uses a single-instruction multiple-thread (SIMT) processing architecture.

29. The GPU of claim 28, wherein:

the electronic device comprises a mobile electronic device;

the micro-code comprises a sequence of micro-coded instructions; and

the at least one processing element is configured to process the micro-code to;

switch an instruction pipeline of the GPU from a first mode to a second mode, the second mode providing control of the instruction pipeline for iterative processing of the micro-code; and

in response to processing the micro-code, switch the instruction pipeline to the first mode for pipelined processing of the instruction pipeline.