Vector floating point test data class immediate instruction

• US 9,471,308 B2
• Filed: 01/23/2013
• Issued: 10/18/2016
• Est. Priority Date: 01/23/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Schwarz, Eric M.
• Primary Examiner(s): Snyder, Steven
• Application Number:
  US13/748,477
• Publication Number:
  US 20140208077A1
• Time in Patent Office: 1,364 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode

Abstract

A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.

Claims

1. A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

at least one opcode field to provide an opcode, the opcode identifying a Vector Floating Point Test Data Class Immediate operation;

a first register field to be used to designate a first register, the first register comprising a first operand; and

a second register field to be used to designate a second register, the second register comprising a second operand; and

a mask field; and

executing the machine instruction, the executing comprising;

determining properties of a chosen element of the second operand, wherein the mask field indicates whether one or more elements of the second operand are to be included in the determining;

selecting from an input to the machine instruction a selected data unit representing the properties of the chosen element, the input including one or more data units to represent one or more properties;

checking whether the selected data unit is set to a particular value; and

based on the checking, setting an element in the first operand that corresponds to the chosen element of the second operand, the setting based on whether the selected data unit is set to the particular value.

2. The computer program product of claim 1, wherein the second operand comprises a plurality of elements, wherein the determining comprises determining properties for each element of the plurality of elements, and wherein the setting comprises setting each element in the first operand corresponding to each element in the second operand based on whether the selected data unit is set to the particular value.

3. The computer program product of claim 1, wherein the setting comprises setting the element in the first operand to ones based on the checking indicating the selected data unit is set to the particular value, and setting the element in the first operand to zero based on the checking indicating the selected data unit is not set to the particular value.

4. The computer program product of claim 1, wherein the properties comprise a class and a sign.

5. The computer program product of claim 1, wherein the input comprises a plurality of data units, each data unit of the plurality of data units representing a class and a sign.

6. The computer program product of claim 5, wherein the plurality of data units comprises a plurality of bits, and wherein each bit represents one element class of a plurality of element classes, the plurality of element classes comprising zero, normal number, subnormal number, infinity, quiet not-a-number, signaling not-a-number, and each bit represents a sign of positive or negative.

7. The computer program product of claim 1, wherein the machine instruction further comprises a field including the input.

8. The computer program product of claim 1, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register and the second register field is combined with a second portion of the extension field to designate the second register.

9. The computer program product of claim 1, wherein the machine instruction further comprises another mask field, the another mask field to indicate a size of a floating point number in an element of the second operand.

10. The computer program product of claim 1, wherein the executing further comprises setting a condition code for the machine instruction, the condition code to summarize the setting of the elements of the first operand.

11. A computer system for executing a machine instruction in a central processing unit, the computer system comprising:

a memory; and

a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising;

obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

at least one opcode field to provide an opcode, the opcode identifying a Vector Floating Point Test Data Class Immediate operation;

a first register field to be used to designate a first register, the first register comprising a first operand;

a second register field to be used to designate a second register, the second register comprising a second operand; and

a mask field; and

executing the machine instruction, the executing comprising;

determining properties of a chosen element of the second operand, wherein the mask field indicates whether one or more elements of the second operand are to be included in the determining;

selecting from an input to the machine instruction a selected data unit representing the properties of the chosen element, the input including one or more data units to represent one or more properties;

checking whether the selected data unit is set to a particular value; and

based on the checking, setting an element in the first operand that corresponds to the chosen element of the second operand, the setting based on whether the selected data unit is set to the particular value.

12. The computer system of claim 11, wherein the second operand comprises a plurality of elements, wherein the determining comprises determining properties for each element of the plurality of elements, and wherein the setting comprises setting each element in the first operand corresponding to each element in the second operand based on whether the selected data unit is set to the particular value.

13. The computer system of claim 11, wherein the setting comprises setting the element in the first operand to ones based on the checking indicating the selected data unit is set to the particular value, and setting the element in the first operand to zero based on the checking indicating the selected data unit is not set to the particular value.

14. The computer system of claim 11, wherein the input comprises a plurality of data units, each data unit of the plurality of data units representing a class and a sign.

15. The computer system of claim 11, wherein the machine instruction further comprises a field including the input.

16. The computer system of claim 11, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register and the second register field is combined with a second portion of the extension field to designate the second register.

17. The computer system of claim 11, wherein the machine instruction further comprises another mask field, the another mask field to indicate a size of a floating point number in an element of the second operand.