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Vector checksum instruction

  • US 9,471,311 B2
  • Filed: 12/09/2014
  • Issued: 10/18/2016
  • Est. Priority Date: 01/23/2013
  • Status: Active Grant
First Claim
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1. A method of executing a machine instruction in a central processing unit, the method comprising:

  • obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

    at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation;

    a first register field to be used to designate a first register, the first register comprising a first operand;

    a second register field to be used to designate a second register, the second register comprising a second operand; and

    an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register;

    and executing the machine instruction, the executing comprising;

    adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations;

    based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and

    placing the first result in the selected element of the first operand.

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