Flash memory controller having dual mode pin-out
First Claim
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1. A dual interface flash memory controller, comprising:
- a NAND flash memory interface havinga first memory interface port including a single pad for communicating information with a memory, the first memory interface port including circuitry configured to provide a first signal compatible for communicating with the memory configured for a multi-drop bus architecture in a first memory interface protocol and configured to receive a second signal compatible for communicating with the memory configured for a serial point-to-point bus architecture in a second memory interface protocol different than the first memory interface protocol, the circuitry including a first signal path configured to drive the first signal, and a second signal path configured to buffer the second signal;
a second memory interface port including first input circuitry configured for receiving an input signal corresponding to the first memory interface protocol from a second single pad, and second input circuitry configured for receiving another input signal corresponding to the second memory interface protocol from the second single pad;
mode selector circuitry for enabling the first signal path or the second signal path in response to an applied voltage level;
and,a host interface having host interface ports for communicating information between a host device and the memory controller.
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Abstract
A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.
148 Citations
15 Claims
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1. A dual interface flash memory controller, comprising:
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a NAND flash memory interface having a first memory interface port including a single pad for communicating information with a memory, the first memory interface port including circuitry configured to provide a first signal compatible for communicating with the memory configured for a multi-drop bus architecture in a first memory interface protocol and configured to receive a second signal compatible for communicating with the memory configured for a serial point-to-point bus architecture in a second memory interface protocol different than the first memory interface protocol, the circuitry including a first signal path configured to drive the first signal, and a second signal path configured to buffer the second signal; a second memory interface port including first input circuitry configured for receiving an input signal corresponding to the first memory interface protocol from a second single pad, and second input circuitry configured for receiving another input signal corresponding to the second memory interface protocol from the second single pad; mode selector circuitry for enabling the first signal path or the second signal path in response to an applied voltage level; and, a host interface having host interface ports for communicating information between a host device and the memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A non-volatile memory system, comprising:
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a NAND flash memory controller including a channel control module having a first input/output port including a single pad with circuitry configured to provide a first signal corresponding to a first memory interface protocol pinout and configured to receive a second signal corresponding to a second memory interface protocol pinout, the circuitry including a first signal path configured to drive the first signal, and a second signal path configured to buffer the second signal; a second input/output port including first input circuitry configured for receiving an input signal corresponding to the first memory interface protocol from a second single pad, and second input circuitry configured for receiving another input signal corresponding to the second memory interface protocol from the second single pad; mode selector circuitry for enabling the first signal path or the second signal path in response to an applied voltage level; and, at least one NAND flash memory configured for a multi-drop bus architecture or configured for a serial point-to-point bus architecture having either the first memory interface protocol pinout or the second memory interface protocol pinout in communication with the channel control module through the first input/output port and the second input/output port. - View Dependent Claims (12, 13, 14, 15)
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Specification