Dynamically controlling cache size to maximize energy efficiency

• US 9,471,490 B2
• Filed: 08/31/2015
• Issued: 10/18/2016
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Weissmann, Eliezer, Rajwan, Doron, Shulman, Nadav, Naveh, Alon, Abu-Salah, Hisham
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US14/840,639
• Publication Number:
  US 20160011975A1
• Time in Patent Office: 414 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first domain including a plurality of cores to independently execute instructions;

a second domain including at least one graphics engine;

a cache memory coupled to the plurality of cores and including a plurality of partitions; and

a power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.

2. The processor of claim 1, wherein the plurality of partitions correspond to ways of the cache memory, and wherein the power controller is to dynamically enable or disable each of a plurality of ways independently.

3. The processor of claim 2, wherein the power controller is to cause at least one first way of the cache memory to be enabled with the retention voltage when the processor is in the package low power state.

4. The processor of claim 3, wherein the power controller is to cause at least one second way of the cache memory to be disabled while the at least one first way is enabled with the retention voltage when the processor is in the package low power state, wherein the at least one second way is to be flushed to a system memory prior to being disabled.

5. The processor of claim 4, wherein the power controller is to power gate the at least one second way.

6. The processor of claim 1, wherein the first domain is to operate at a first voltage and a first frequency and the second domain is to operate at a second voltage and a second frequency.

7. The processor of claim 1, wherein the processor comprises a first die including the first domain and a second die including the second domain.

8. The processor of claim 1, wherein the processor comprises a package including a first semiconductor die and a second semiconductor die.

9. The processor of claim 1, wherein the cache memory comprises a last level cache memory.

10. The processor of claim 1, wherein the cache memory comprises a coherent static random access memory.

11. The processor of claim 1, further comprising a ring interconnect to couple the plurality of cores to the cache memory, the cache memory comprising a shared cache memory.

12. The processor of claim 1, wherein the first logic is to determine the memory boundedness based on a memory boundedness ratio comprising a ratio of average load residency in an order buffer to active state residency.

13. The processor of claim 12, wherein the order buffer includes a plurality of entries each having a field to store a count of cycles in which an instruction is pending in the entry.

14. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

determining, in a power controller of a multicore processor, whether a memory dependency value of a workload is greater than a first threshold, and if so enabling all of a plurality of ways of a cache memory of the multicore processor; and

otherwise determining, in the power controller, if the memory dependency value is less than a third threshold, and if so disabling at least one way of the cache memory.

15. The non-transitory machine-readable medium of claim 14, wherein the method further comprises enabling at least one more way of the cache memory if the memory dependency value is greater than a second threshold, the second threshold between the first and third thresholds.

16. The non-transitory machine-readable medium of claim 14, wherein the method further comprises calculating the memory dependency value of the workload, including determining an order buffer residency during a time interval.

17. The non-transitory machine-readable medium of claim 16, further comprising:

determining an average of a plurality of counters, each counter of an entry of the order buffer;

calculating a ratio between the average and a length of the time interval; and

controlling a size of the cache memory based at least in part on the ratio.

18. A system comprising:

a processor comprising;

a plurality of cores to independently execute instructions;

a shared cache memory coupled to the plurality of cores and including a plurality of partitions; and

a power controller coupled to the plurality of cores and the shared cache memory, wherein the power controller includes a first logic to dynamically vary a size of the shared cache memory based on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least a first partition to be powered with a retention voltage to maintain a state of at least one core of the plurality of cores and cause at least a second partition to be disabled while the at least first partition is powered with the retention voltage when the processor is in a package low power state in which the plurality of cores are power gated, the power controller to dynamically enable or disable the plurality of partitions independently;

at least one graphics engine; and

an interconnect to couple the plurality of cores, the shared cache memory, and the

at least one graphics engine;

at least one communication device coupled to the processor; and

a system memory coupled to the processor.

19. The system of claim 18, wherein the power controller is to determine a size of the shared cache memory to remain powered on based at least in part on a duration of the package low power state.

20. The system of claim 18, wherein the power controller is to operate at a fixed frequency during normal operation and at a reduced frequency during the package low power state.