Demote instruction for relinquishing cache line ownership

• US 9,471,503 B2
• Filed: 02/11/2016
• Issued: 10/18/2016
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shum, Chung-Lung Kevin, Jackson, Kathryn Marie, Webb, Charles Franklin
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US15/041,448
• Publication Number:
  US 20160196213A1
• Time in Patent Office: 250 Days
• Field of Search: 711/141, 711/144, 711/145, 711/121, 711/146
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer system processor of a multi-processor computer system having a cache subsystem, the computer system having exclusive ownership of a cache line, executes a demote instruction to cause its own exclusively owned cache line to become shared or read-only in the computer processor cache.

Claims

1. A computer system for relinquishing, by a selected processor, the selected processor'"'"'s own exclusive ownership of a specified cache line, the system comprising:

a multi-processor system comprising the selected processor, each processor of the multi-processor system comprising a private cache, the selected processor being an out-of-order processor comprising a pipeline and a selected private cache, the selected processor configured to perform a method comprising;

executing, by the selected processor, a demote instruction of a software program, the demote instruction specifying a logical address of the specified cache line, the executing the demote instruction by the selected processor causing a method to be performed comprising;

translating, by the selected processor, the logical address to a cache address;

based on the demote instruction specified logical address, determining, by the selected processor, whether the specified cache line is exclusively owned in the selected private cache of the selected processor; and

based on the demote instruction in the pipeline not being in an incorrectly predicted branch path, and no older instruction, older than the demote instruction, in the pipeline not completing due to being flushed from the pipeline, and the selected processor determining that the specified cache line is exclusively owned in the selected private cache of the selected processor, relinquishing exclusive ownership, in the selected private cache, of the specified cache line by the selected processor.

2. The computer system according to claim 1, wherein the cache address of the specified cache line is an absolute address.

3. The computer system according to claim 1, wherein execution of the demote instruction, by the selected processor, performs no architectural update.

4. The computer system according to claim 1, wherein, based on the executing the demote instruction, by the selected processor, the selected processor completes all pending stores to the specified cache line before relinquishing the exclusive ownership of the cache line.

5. The computer system according to claim 1, wherein the relinquishing the exclusive ownership of the specified cache line, by the selected processor, comprises setting, by the selected processor, the ownership of the specified cache line of the selected private cache to any one of shared or read-only.

6. The computer system according to claim 1, wherein the relinquishing the exclusive ownership of the specified cache line, by the selected processor, comprises allowing another processor of the multiprocessor system to immediately be given exclusive ownership to the specified cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement.

7. The computer system according to claim 1, wherein prior to the executing the demote instruction, by the selected processor, a method is performed, by the selected processor, comprising:

obtaining, by the selected processor, the exclusive ownership of the specified cache line; and

performing, by the selected processor having the exclusive ownership of the specified cache line, a store operation to the specified cache line of the selected private cache.