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Computing system automatically generating a transactor

  • US 9,471,736 B2
  • Filed: 02/26/2015
  • Issued: 10/18/2016
  • Est. Priority Date: 05/22/2014
  • Status: Active Grant
First Claim
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1. A system-on-chip (SoC) bus verification device for verifying a bus of an SoC, comprising:

  • a memory device configured to store a file list for the SoC including a design file associated with an intellectual property (IP) and a transactor generating tool; and

    a processor configured to execute the transactor generating tool stored in the memory device, wherein the transactor generating tool when executed by the processor causes the processor to;

    extract port information for the IP from the design file;

    generate at least one transactor associated with the IP based on the port information; and

    replace the design file of the IP included in the file list for the SoC with an empty design file and the generated transactor.

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