Sense amplifier and related method

• US 9,472,245 B2
• Filed: 12/31/2013
• Issued: 10/18/2016
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Po-Hao, Chou, Chung-Cheng
• Primary Examiner(s): Norman, James G
• Application Number:
  US14/145,700
• Publication Number:
  US 20150187394A1
• Time in Patent Office: 1,022 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is electrically connected to the first current mirror, and a second inverter is electrically connected to the second current mirror. The first and second inverters are cross-coupled.

Claims

1. A device comprising:

a first current mirror electrically connected to a reference current source of a memory array;

a second current mirror electrically connected to a cell current source of the memory array, wherein the first current mirror and the second current mirror have an equivalent structure;

a first inverter having;

a first input terminal electrically connected to the first current mirror; and

a first output terminal; and

a second inverter having;

a second input terminal electrically connected to the second current mirror and the first output terminal; and

a second output terminal electrically connected to the first current mirror and the first input terminal;

a first clamp transistor directly connected to the first current mirror and a first select transistor;

a second clamp transistor electrically connected to the second current mirror and a second select transistor;

the first select transistor directly connected to the first clamp transistor and the reference current source; and

a second select transistor electrically connected to the second clamp transistor and the cell current source.

2. The device of claim 1, wherein:

the first inverter has;

a first transistor;

a second transistor having a gate electrode electrically connected to a gate electrode of the first transistor; and

a first enable transistor having a source electrode electrically connected to a drain electrode of the first transistor, and a drain electrode electrically connected to a drain electrode of the second transistor; and

the second inverter has;

a third transistor;

a fourth transistor having a gate electrode electrically connected to a gate electrode of the third transistor; and

a second enable transistor having a source electrode electrically connected to a drain electrode of the third transistor, and a drain electrode electrically connected to a drain electrode of the fourth transistor.

3. The device of claim 1, further comprising:

a first pre-charge transistor electrically connected to the first input terminal; and

a second pre-charge transistor electrically connected to the second input terminal.

4. The device of claim 1, wherein the first current mirror comprises:

a first current mirror transistor, a source terminal of the first current mirror transistor being directly connected to a voltage supply, a drain terminal of the first current mirror transistor being connected to a clamp transistor; and

a second current mirror transistor, a gate terminal of the second current mirror transistor being connected to a gate of the first current mirror transistor, and a source terminal of the second current mirror transistor being directly connected to the voltage supply.

5. The device of claim 1, wherein a gate terminal of the first clamp transistor is electrically connected to a gate terminal of the second clamp transistor.

6. The device of claim 2, further comprising:

a third inverter having an input terminal electrically connected to the first output terminal; and

a fourth inverter having an input terminal electrically connected to the drain electrode of the fourth transistor.

7. A device comprising:

at least two sense amplifier blocks, each sense amplifier block including;

a first multiplexer having at least two inputs electrically connected to first bit cells of a memory array;

a second multiplexer having at least two inputs electrically connected to second bit cells of the memory array, the second multiplexer being physically disconnected from the first multiplexer;

a reference current source having;

a first reference line electrically connected to a first reference bit cell; and

a second reference line electrically connected to a second reference bit cell;

a first sense amplifier having a first input electrically connected to an output of the first multiplexer, and a second input electrically connected to a first output terminal of the reference current source; and

a second sense amplifier having a first input electrically connected to an output of the second multiplexer, and a second input electrically connected to a second output terminal of the reference current source; and

at least one switch configured to merge reference currents supplied through the first and second reference lines of the at least two sense amplifier blocks, wherein the merged reference currents continuously pass along a same conductive path, the conductive path extending to each of the at least two sense amplifier blocks.

8. The device of claim 7, wherein each of the first and second sense amplifiers comprises:

a first current mirror electrically connected to the reference current source;

a second current mirror electrically connected to the first or second multiplexer;

a first inverter having;

a first input terminal electrically connected to the first current mirror;

a first output terminal; and

a second inverter having;

a second input terminal electrically connected to the second current mirror and the first output terminal; and

a second output terminal electrically connected to the first current mirror and the first input terminal.

9. The device of claim 8, wherein:

the first inverter has;

a first transistor;

a second transistor having a gate electrode electrically connected to a gate electrode of the first transistor; and

a first enable transistor having a source electrode electrically connected to a drain electrode of the first transistor, and a drain electrode electrically connected to a drain electrode of the second transistor; and

the second inverter has;

a third transistor;

a fourth transistor having a gate electrode electrically connected to a gate electrode of the third transistor; and

a second enable transistor having a source electrode electrically connected to a drain electrode of the third transistor, and a drain electrode electrically connected to a drain electrode of the fourth transistor.

10. The device of claim 8, wherein each of the first and second sense amplifiers further comprises:

a first pre-charge transistor electrically connected to the first input terminal; and

a second pre-charge transistor electrically connected to the second input terminal.

11. The device of claim 8, wherein each of the first and second sense amplifiers further comprises:

first clamp transistor electrically connected to the first current mirror and the reference current source; and

a second clamp transistor electrically connected to the second current mirror and a memory cell.

12. The device of claim 11, wherein each of the first and second sense amplifiers further comprises:

a first select transistor electrically connected to the first clamp transistor and the reference current source; and

a second select transistor electrically connected to the second clamp transistor and the memory cell.

13. The device of claim 8, wherein each of the first and second sense amplifiers further comprises:

a third inverter having an input terminal electrically connected to the first output terminal; and

a fourth inverter having an input terminal electrically connected to the second output terminal.

14. A method comprising:

(a) receiving a reference current;

(b) mirroring the reference current to generate a mirrored reference current;

(c) receiving a cell current;

(d) mirroring the cell current to generate a mirrored cell current;

(e) receiving a first sense amplifier enable signal from a controller by a first transistor and a second transistor of a sense amplifier, a drain electrode of the first transistor being directly connected to a current mirror that mirrors the cell current and a drain electrode of the second transistor being directly connected to a current mirror that mirrors the reference current, the first sense amplifier enable signal having a voltage that is sufficiently high to turn off the first transistor and the second transistor;

(f) charging a first input node of the sense amplifier to a first voltage by the mirrored reference current;

(g) charging a second input node of the sense amplifier to a second voltage by the mirrored cell current;

(h) receiving a second sense amplifier enable signal by the first transistor and the second transistor of the sense amplifier, the second sense amplifier enable signal having a voltage that is sufficiently low to turn on the first transistor and the second transistor; and

(i) latching the first and second voltages.

15. The method of claim 14, further comprising:

(j) discharging the first and second input nodes of the sense amplifier to a third voltage prior to (e) and (f).

16. The method of claim 14, wherein (a) includes receiving the reference current from a reference current source shared between the sense amplifier and another sense amplifier.

17. The method of claim 14, further comprising:

(k) outputting a differential sense signal by inverting the first voltage by a first inverter and inverting the second voltage by a second inverter.

18. The method of claim 14, wherein (c) includes receiving the cell current generated by a resistive random access memory (RRAM) bit cell.

19. The method of claim 14, wherein (a) includes receiving the reference current from a reference current source shared between the sense amplifier and at least three other sense amplifiers.

20. The method of claim 14, wherein (a) includes receiving a merged current including first current from a first bit cell programmed to binary “

1” and

second current from a second bit cell programmed to binary “

0”

.