Memory, semiconductor device including the same, and method for testing the same

• US 9,472,247 B2
• Filed: 02/13/2015
• Issued: 10/18/2016
• Est. Priority Date: 02/13/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Cheng-Hsiung, Li, Gu-Huan, Chen, Chung-Chieh, Wang, Jih-Chen
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US14/621,521
• Publication Number:
  US 20160240233A1
• Time in Patent Office: 613 Days
• Field of Search: 365/189.05
• US Class Current: 1/1
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/18 Circuits for erasing optically
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.

Claims

1. A memory comprising:

a first memory cell;

a second memory cell;

a latch unit having a true node and a complement node; and

a switch unit responsive to a first control signal and a second control signal, and configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal.

2. The memory of claim 1, wherein the switch unit includes a normally-closed switch connected between the first memory cell and the true node, and another normally-closed switch connected between the second memory cell and the complement node.

3. The memory of claim 1, further comprising a contact, wherein the switch unit is further configured to connect and disconnect the contact to the complement node and from the true node in response to the first control signal and to connect and disconnect the contact to the true node and from the complement node in response to the second control signal.

4. The memory of claim 3, wherein the switch unit includes a normally-open switch connected between the contact and the true node, and another normally-open switch connected between the contact and the complement node.

5. The memory of claim 1, further comprising a current source circuit, wherein the switch unit is further configured to connect and disconnect the current source circuit to the complement node and from the true node in response to the first control signal, and to connect and disconnect the current source circuit to the true node and from the complement node in response to the second control signal.

6. The memory of claim 5, wherein the switch unit includes a normally-open switch connected between the current source circuit and the true node, and another normally-open switch connected between the current source circuit and the complement node.

7. A semiconductor device comprising:

a first memory cell;

a second memory cell;

a latch unit having a first node and a second node;

a switch unit; and

a control unit connected to the switch unit and configured to generate a first control signal and a second control signal, wherein the switch unit is responsive to the first and second control signals, and is configured to connect the first memory cell to the first node and to disconnect the second memory cell from the second node in response to the first control signal and to connect the second memory cell to the second node and to disconnect the first memory cell from the first node in response to the second control signal.

8. The semiconductor device of claim 7, wherein the switch unit includes a normally-closed switch connected between the first memory cell and the first node.

9. The semiconductor device of claim 7, wherein the switch unit includes a normally-closed switch connected between the second memory cell and the second node.

10. The semiconductor device of claim 7, further comprising a contact, wherein the switch unit is further configured to connect and disconnect the contact to the second node and from the first node in response to the first control signal and to connect and disconnect the contact to the first node and from the second node in response to the second control signal.

11. The semiconductor device of claim 10, wherein the switch unit includes a normally-open switch connected between the contact and the first node, and another normally-open switch connected between the contact and the second node.

12. The semiconductor device of claim 7, further comprising a current source circuit, wherein the switch unit is further configured to connect and disconnect the current source circuit to the second node and from the first node in response to the first control signal and to connect and disconnect the current source circuit to the first node and from the second node in response to the second control signal.

13. The semiconductor device of claim 12, wherein the switch unit includes a normally-open switch connected between the current source circuit and the first node, and another normally-open switch connected between the current source circuit and the second node.

14. A method for testing a memory of a semiconductor device, the method comprising:

in response to a first control signal, a switch unit connecting a first memory cell to a true node of a latch unit and disconnecting a second memory cell from a complement node of the latch unit; and

in response to a second control signal, the switch unit connecting the second memory cell to the complement node and disconnecting the first memory cell from the true node.

15. The method of claim 14, further comprising:

in response to the first control signal, the switch unit connecting and disconnecting a contact to the complement node and from the true node; and

in response to the second control signal, the switch unit connecting and disconnecting the contact to the true node and from the complement node.

16. The method of claim 14, further comprising:

in response to the first control signal, the switch unit connecting and disconnecting a current source circuit to the complement node and from the true node; and

in response to the second control signal, the switch unit connecting and disconnecting the current source circuit to the true node and from the complement node.

17. The method of claim 14, further comprising:

in response to a first input signal, a control unit generating the first control signal; and

in response to a second input signal, the control unit generating the second control signal.

18. The method of claim 14, further comprising:

the first memory cell generates a cell current that flows to the true node; and

the latch unit generates a voltage, and an output signal that corresponds to the voltage.

19. The method of claim 14, further comprising:

the second memory cell generates a cell current that flows to the complement node; and

the latch unit generates a voltage, and an output signal that corresponds to the voltage.