Magnetic memory having two transistors and two magnetic tunnel junctions per memory cell

• US 9,472,256 B1
• Filed: 10/01/2015
• Issued: 10/18/2016
• Est. Priority Date: 10/01/2014
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Andre, Thomas
• Primary Examiner(s): Yang, Han
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US14/872,678
• Time in Patent Office: 383 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

Circuits and methods for driving generating multiple word line voltages used for writing to two-transistor two-magnetic tunnel junction (2T2MTJ) spin-torque magnetic random access memory (MRAM) cells. Some embodiments include auto-booting isolated word lines using common lines such as bit and source lines that are capacitively coupled to the word lines. Different memory architectures for 2T2MTJ memory arrays are also presented that include read/write circuits and word line drivers.

Claims

1. A magnetoresistive memory, comprising:

a first memory cell that includes;

a first select device;

a first magnetic tunnel junction coupled in series with the first select device;

a second select device; and

a second magnetic tunnel junction coupled in series with the second select device, wherein the first memory cell is configured to store a single bit by storing complementary states in the first and second magnetic tunnel junctions;

a first word line coupled to the first select device;

a second word line coupled to the second select device; and

a first circuit configured to generate a first voltage on the first word line and a second voltage on the second word line, wherein the second voltage is greater in magnitude than the first voltage.

2. The magnetoresistive memory of claim 1, wherein:

the first select device is included in a first plurality of select devices in an even column of an array; and

the second select device is included in a second plurality of select devices in an odd column of the array.

3. The magnetoresistive device of claim 1 further comprising a first read circuit coupled to the first and second magnetic tunnel junctions, wherein the first read circuit is configured to determine the single bit stored in the first memory cell based on the complementary states stored in the first and second magnetic tunnel junctions.

4. The magnetoresistive device of claim 3, wherein characteristics of signal routing between the first magnetic tunnel junction and the first read circuit is substantially similar to characteristics of signal routing between the second magnetic tunnel junction and the first read circuit.

5. The magnetoresistive device of claim 3, wherein the first read circuit is physically between the first and second magnetic tunnel junctions in the magnetoresistive device.

6. The magnetoresistive device of claim 3, wherein the first circuit is further configured to receive an enable signal and apply the first voltage to the first and second word lines based on the enable signal.

7. The magnetoresistive device of claim 6, wherein the first circuit is further configured to:

after applying the first voltage to the second word line based on the enable signal, isolate the second word line from a source of the first voltage, wherein the second voltage is achieved on the second word line while the second word line is isolated.

8. The magnetoresistive device of claim 7, wherein the first circuit is further configured to use the second voltage on the second word line to maintain the first voltage on the first word line.

9. The magnetoresistive device of claim 6, further comprising:

a second memory cell that includes;

a third select device;

a third magnetic tunnel junction coupled in series with the third select device;

a fourth select device; and

a fourth magnetic tunnel junction coupled in series with the fourth select device; and

a second read circuit coupled to the third and fourth magnetic tunnel junctions, wherein the second read circuit is configured to determine a single bit stored in the second memory cell based on complementary states stored in the third and fourth magnetic tunnel junctions.

10. The magnetoresistive device of claim 9, further comprising:

a third word line coupled to the third select device;

a fourth word line coupled to the fourth select device; and

a second circuit configured to generate the first voltage on the third word line and the second voltage on the fourth word line.

11. The magnetoresistive device of claim 10, wherein the second circuit is further configured to receive the enable signal and apply the first voltage to the third and fourth word lines based on the enable signal.

12. The magnetoresistive device of claim 1 wherein the first voltage is greater in magnitude than a power supply voltage.

13. The magnetoresistive device of claim 1, further comprising a plurality of common lines capacitively coupled to the second word line, wherein the first circuit is configured to generate the second voltage on the second word line, wherein generating the second voltage on the second word line includes:

after driving the second word line to the first voltage, isolating the second word line from a source of the first voltage; and

after isolating the second word line, driving the plurality of common lines to a voltage greater than the first voltage such that the second word line is raised to the second voltage as a result of capacitive coupling between the plurality of common lines and the second word line.

14. The magnetoresistive memory of claim 1, wherein the first circuit is configured to:

generate the first voltage on the first word line such that the first select device allows current flow through the first magnetic tunnel junction device; and

generate the second voltage on the second word line such that the second select device allows current flow through the second magnetic tunnel junction device.

15. The magnetoresistive memory of claim 14, wherein the first circuit is further configured to use the second voltage on the second word line to maintain the first voltage on the first word line.

16. A magnetoresistive memory, comprising:

a first memory cell that includes;

a first select device;

a first magnetic tunnel junction coupled in series with the first select device;

a second select device; and

a second magnetic tunnel junction coupled in series with the second select device, wherein the first memory cell is configured to store a single bit by storing complementary states in the first and second magnetic tunnel junctions;

a first word line coupled to the first select device;

a second word line coupled to the second select device;

a plurality of common signal lines capacitively coupled to the second word line; and

a circuit configured to;

drive a first voltage on the first word line;

drive the first voltage on the second word line;

after driving the first voltage on the second word line, isolating the second word line from a source of the first voltage;

after isolating the second word line, driving a second voltage on the plurality of common signal lines such that the second word line is boosted to a third voltage as a result of capacitive coupling between the plurality of common lines and the second word line, wherein the third voltage is greater in magnitude than the first voltage.

17. The magnetoresistive memory of claim 16 further comprising current generation circuitry coupled to the first and second magnetic tunnel junctions, the current generation circuitry configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction, where the first write current flows through the first select device before the first magnetic tunnel junction and the second write current flows through the second magnetic tunnel junction before the second select device.

18. The magnetoresistive memory of claim 17, wherein the circuit is further configured to use the third voltage on the second word line to maintain the first voltage on the first word line.

19. The magnetoresistive memory of claim 17 further comprising:

a read circuit coupled to the first and second magnetic tunnel junctions, wherein the read circuit is configured to determine, during a read operation, the single bit stored in the first memory cell based on the complementary states stored in the first and second magnetic tunnel junctions.

20. The magnetoresistive memory of claim 19, wherein during the read operation:

the current generation circuitry generates a read current through each of the first and second magnetic tunnel junctions; and

the circuit drives the first voltage on both the first and second word lines.