Memory controller

• US 9,472,262 B2
• Filed: 03/15/2016
• Issued: 10/18/2016
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US15/070,376
• Publication Number:
  US 20160196864A1
• Time in Patent Office: 217 Days
• Field of Search: 365/194, 365/191, 365/193, 365/233.1, 365/221
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Claims

1. A memory controller component comprising:

transmit circuitry to transmit, to a dynamic random access memory device (DRAM);

write data to be sampled by the DRAM in response to a timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM in response to the first clock signal, the write command associated with the write data; and

adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that an edge transition of the timing signal at the DRAM is aligned with an edge transition of the first clock signal at the DRAM.

2. The memory controller component of claim 1, wherein the write data accompanies the timing signal while the write data and the timing signal propagate from the memory controller component to the DRAM.

3. The memory controller component of claim 1, wherein the timing signal is a strobe signal.

4. The memory controller component of claim 1, wherein the timing signal is a second clock signal.

5. The memory controller component of claim 1, wherein the transmit timing of the write data is adjusted by an amount that increases a signaling margin of the write data being sampled by the DRAM.

6. The memory controller component of claim 1, wherein the adjusting circuitry comprises circuitry to adjust a phase of a transmit clock signal that times transmission of the write data.

7. The memory controller component of claim 1, wherein the adjusting circuitry comprises clock generation circuitry to generate a plurality of phase-distributed clock signals and an internal clock signal, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of the internal clock signal, wherein the memory controller adjusts the transmit timing of the write data using clock signals selected from the plurality of phase-distributed clock signals.

8. The memory controller of claim 7, wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the internal clock signal based on a reference clock signal that has a lower frequency than the internal clock signal.

9. The memory controller component of claim 7, wherein the adjusting circuitry further comprises a plurality of phase offset selection circuits, and wherein a phase offset selection circuit of the plurality of phase offset selection circuits selects a phase-distributed clock signal from the plurality of phase-distributed clock signals to be a timing reference for transmission of the write data.

10. The memory controller of component of claim 9, wherein the phase offset selection circuit comprises a multiplexer to select the phase-distributed clock signal.

11. The memory controller component of claim 9, wherein the phase offset selection circuit comprises a phase interpolator to select the phase-distributed clock signal.

12. The memory controller component of claim 1, wherein the first clock signal is provided to the memory controller component from an external clock signal generator circuit.

13. The memory controller component of claim 1, wherein the transmit circuitry comprises:

a first transmitter circuit to transmit the first clock signal; and

a second transmitter circuit to transmit the write command, wherein transmission of the write command is timed using the first clock signal.

14. A method of operation of a memory controller component, the method comprising:

transmitting, to a dynamic random access memory device (DRAM);

write data to be sampled by the DRAM in response to a timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM in response to the first clock signal, the write command associated with the write data; and

adjusting transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that an edge transition of the timing signal at the DRAM is aligned with an edge transition of the first clock signal at the DRAM.

15. The method of claim 14, wherein the write data accompanies the timing signal while the write data and the timing signal propagate from the memory controller component to the DRAM.

16. The method of claim 14, wherein the timing signal is a strobe signal.

17. The method of claim 14, wherein the timing signal is a second clock signal.

18. The method of claim 14, wherein the transmit timing of the write data is adjusted by an amount that increases a signaling margin of the write data being sampled by the DRAM.

19. The method of claim 14, further comprising adjusting a phase of a transmit clock signal that times transmission of the write data based on a difference between the first and second time intervals.

20. A memory controller component comprising:

means for transmitting, to a dynamic random access memory device (DRAM);

write data to be sampled by the DRAM in response to a timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM in response to the first clock signal, the write command associated with the write data; and

means for adjusting transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that an edge transition of the timing signal at the DRAM is aligned with an edge transition of the first clock signal at the DRAM.