Voltage generator, oscillation device and operation method

• US 9,472,278 B2
• Filed: 09/30/2014
• Issued: 10/18/2016
• Est. Priority Date: 01/08/2014
• Status: Active Grant

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: Wang, Cheng-Chih
• Primary Examiner(s): Tan, Richard
• Application Number:
  US14/501,049
• Publication Number:
  US 20150194928A1
• Time in Patent Office: 749 Days
• Field of Search: 331/57, 331/177.R, 331/185, 331/186, 365/100, 365/148, 365/158, 365/159, 365/242
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A voltage generator and an oscillation device, and an operation method thereof are disclosed. The oscillation device includes a non-volatile memory, the voltage generator and a voltage-controlled oscillation (VCO) circuit. The voltage generator uses the non-volatile resistance provided by a non-volatile memory to generate a bias voltage. The VCO circuit is coupled to the voltage generator so as to generate a corresponding oscillation frequency based on the bias voltage.

Claims

1. An oscillation device, comprising:

at least one non-volatile memory;

a voltage generator, comprising a current source for providing a current flowing through the at least one non-volatile memory, for generating a bias voltage by using a non-volatile resistance of the at least one non-volatile memory; and

a voltage-controlled oscillation (VCO) circuit, coupled to the voltage generator and configured to generate a corresponding oscillation frequency based on the bias voltage,

wherein the non-volatile resistance of the at least one non-volatile memory is set independently from the current provided by the current source to adjust the bias voltage,

wherein the non-volatile memory is located in the voltage generator, a first terminal and a second terminal of the non-volatile memory are respectively coupled to the current source and a low-level voltage,

wherein the non-volatile memory comprises at least one resistive non-volatile memory (RNVM) cell coupled between the first terminal and the second terminal of the non-volatile memory so as to provide the non-volatile resistance,

wherein the first terminal of the non-volatile memory provides the bias voltage,

wherein the voltage generator further comprises;

a NOT gate, having an input terminal and an output terminal, and the input terminal of the NOT gate receiving a programming signal;

a switch, having a control terminal, a first terminal and a second terminal, the control terminal of the switch being coupled to the output terminal of the NOT gate, the first terminal of the switch being coupled to the first terminal of the non-volatile memory to receive the bias voltage and the second terminal of the switch being coupled to an input terminal of the VCO circuit; and

a capacitor, coupled between the second terminal of the switch and a low-level voltage, wherein during a non-normal operation period, the switch is turned off while the capacitor maintains the bias voltage.

2. The oscillation device according to claim 1, wherein the non-volatile memory is a resistive random access memory or a phase-change random access memory.

3. The oscillation device according to claim 1, wherein the non-volatile resistance of the non-volatile memory is determined by a programming process utilizing a digital signal, and the bias voltage is generated in accordance with the non-volatile resistance and the current provided by the current source.

4. The oscillation device according to claim 1, wherein the bias voltage is varied in accordance with the non-volatile resistance of the non-volatile memory.

5. The oscillation device according to claim 1, wherein the RNVM cells are connected in series or in parallel between the first terminal and the second terminal of the non-volatile memory.

6. The oscillation device according to claim 5, wherein each of the RNVM cells comprises at least one RNVM circuit, and the at least one RNVM circuit is connected in series or in parallel in one of the RNVM cells.

7. The oscillation device according to claim 1, wherein each of the RNVM cells comprises at least one RNVM circuit, and any one of the RNVM circuits comprises:

a resistive memory element, having a first terminal and a second terminal; and

a control circuit, coupled to the first terminal and the second terminal of the resistive memory element and configured to selectively transmit a programming voltage to the first terminal or the second terminal of the resistive memory element in a programming period, or selectively couple the first terminal and the second terminal of the resistive memory element to a first terminal and a second terminal of the RNVM circuit respectively in a normal operation period.

8. The oscillation device according to claim 7, wherein the control circuit comprises:

a switching unit, selectively transmitting the programming voltage to a first terminal of the switching unit and transmitting a low-level voltage to a second terminal of the switching unit, or selectively transmitting the programming voltage to the second terminal of the switching unit and transmitting the low-level voltage to the first terminal of the switching unit, in accordance with a data signal;

a programming unit, coupled to the first terminal and the second terminal of the resistive memory element and the switching unit, and configured to based on a programming signal, selectively couple the first terminal and the second terminal of the switching unit to the first terminal and the second terminal of the resistive memory element respectively in the programming period or selectively disconnect electrically the resistive memory element from the switching unit in the normal operation period; and

an impedance output unit, coupled between the first terminal of the RNVM circuit and the first terminal of the resistive memory element, coupled between the second terminal of the resistive memory element and the second terminal of the RNVM circuit, and configured to based on the programming signal, couple the first terminal of the resistive memory element to the first terminal of the RNVM circuit and couple the second terminal of the resistive memory element to the second terminal of the RNVM circuit in the normal operation period or eclectically disconnect the first terminal of the RNVM circuit from the first terminal of the resistive memory element and electrically disconnect the second terminal of the resistive memory element from the second terminal of the RNVM circuit in the programming period.

9. A voltage generator, comprising:

a current source, providing a current;

a non-volatile memory, having a first terminal and a second terminal respectively coupled to the current source and a low-level voltage, having a non-volatile resistance determined by a programming process, and generating a bias voltage in accordance with the non-volatile resistance and the current, wherein the current flowing through the non-volatile memory,

a NOT gate, having an input terminal and an output terminal, and the input terminal of the NOT gate receiving a programming signal;

a switch, having a control terminal, a first terminal and a second terminal, the control terminal of the switch being coupled to the output terminal of the NOT gate, the first terminal of the switch being coupled to the first terminal of the non-volatile memory to receive the bias voltage, and the second terminal of the switch being coupled to an input terminal of a voltage-controlled oscillation circuit; and

a capacitor, coupled between the second terminal of the switch and a low-level voltage,

wherein during a non-normal operation period, the switch is turned off while the capacitor maintains the bias voltage,

wherein the non-volatile resistance of the at least one non-volatile memory is set independently from the current provided by the current source to adjust the bias voltage.

10. The voltage generator according to claim 9, wherein the non-volatile resistance of the non-volatile memory is determined by the programming process utilizing a digital signal.

11. The voltage generator according to claim 9, wherein the non-volatile memory comprises:

at least one resistive non-volatile memory (RNVM) cell, coupled between the first terminal and the second terminal of the non-volatile memory so as to provide the non-volatile resistance.

12. The voltage generator according to claim 11, wherein each of the RNVM cells comprises at least one RNVM circuit, and any one of the RNVM circuits comprises:

a resistive memory element, having a first terminal and a second terminal; and

a control circuit, coupled to the first terminal and the second terminal of the resistive memory element, and configured to selectively transmit a programming voltage to the first terminal or the second terminal of the resistive memory element in a programming period, or selectively couple the first terminal and the second terminal of the resistive memory element to a first terminal and a second terminal of the RNVM circuit respectively in a normal operation period.

13. The voltage generator according to claim 12, wherein the control circuit comprises:

a switching unit, selectively transmitting the programming voltage to a first terminal of the switching unit and transmitting a low-level voltage to a second terminal of the switching unit or selectively transmitting the programming voltage to the second terminal of the switching unit and transmitting the low-level voltage to the first terminal of the switching unit, in accordance with a data signal;

a programming unit, coupled to the first terminal and the second terminal of the resistive memory element and the switching unit, and configured to based on a programming signal, selectively couple the first terminal and the second terminal of the switching unit respectively to the first terminal and the second terminal of the resistive memory element in the programming period or selectively disconnect electrically the resistive memory element from the switching unit in the normal operation period; and

an impedance output unit, coupled between the first terminal of the RNVM circuit and the first terminal of the resistive memory element, coupled between the second terminal of the resistive memory element and the second terminal of the RNVM circuit, and configured to based on the programming signal, couple the first terminal of the resistive memory element to the first terminal of the RNVM circuit and couple the second terminal of the resistive memory element to the second terminal of the RNVM circuit in the normal operation period or eclectically disconnect the first terminal of the RNVM circuit from the first terminal of the resistive memory element and electrically disconnect the second terminal of the resistive memory element from the second terminal of the RNVM circuit in the programming period.

14. The voltage generator according to claim 13, wherein the switching unit comprises:

a NOT gate, having an input terminal and an output terminal, and the input terminal of the NOT gate receiving a data signal;

a first transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the first transistor being configured to receive the data signal, the first terminal of the first transistor being coupled to the first terminal of the switching unit, and the second terminal of the first transistor being configured to receive the programming voltage;

a second transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the second transistor being coupled to the output terminal of the NOT gate, the first terminal of the second transistor being coupled to the first terminal of the first transistor, and the second terminal of the second transistor being configured to receive the low-level voltage;

a third transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the third transistor being configured to receive the data signal, the first terminal of the third transistor being coupled to the second terminal of the switching unit, and the second terminal of the third transistor being configured to receive the low-level voltage; and

a fourth transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the fourth transistor being coupled to the output terminal of the NOT gate, the first terminal of the fourth transistor being coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor being configured to receive the programming voltage.

15. The voltage generator according to claim 13, wherein the programming unit comprises:

a first transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the first transistor being configured to receive the programming signal, the first terminal of the first transistor being coupled to the first terminal of the resistive memory element, and the second terminal of the first transistor being coupled to the first terminal of the switching unit; and

a second transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the second transistor being configured to receive the programming signal, the first terminal of the second transistor being coupled to the second terminal of the resistive memory element, the second terminal of the second transistor being coupled to the second terminal of the switching unit.

16. The voltage generator according to claim 13, wherein the impedance output unit comprises:

a NOT gate, having an input terminal and an output terminal, and the input terminal of the NOT gate receiving the programming signal;

a first transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the first transistor being coupled to the output terminal of the NOT gate, the first terminal of the first transistor being coupled to the first terminal of the RNVM circuit, and the second terminal of the first transistor being coupled to the first terminal of the resistive memory element; and

a second transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the second transistor being coupled to the output terminal of the NOT gate, the first terminal of the second transistor being coupled to the second terminal of the resistive memory element, and the second terminal of the second transistor being coupled to the second terminal of the RNVM circuit.