Resistive memory device and method of operating the same

• US 9,472,282 B2
• Filed: 12/28/2015
• Issued: 10/18/2016
• Est. Priority Date: 01/06/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yong-Kyu, Lee, Yeong-Taek, Byeon, Dae-Seok, Yoon, Chi-Weon
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US14/979,947
• Publication Number:
  US 20160196876A1
• Time in Patent Office: 295 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.

Claims

1. A resistive memory device comprising:

a memory cell array comprising a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other;

a write circuit connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and to provide pulses to the selected memory cell;

a voltage detector to detect a node voltage at a connection node between the selected first signal line and the write circuit; and

a voltage generation circuit to generate a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and to change a voltage level of the second inhibit voltage based on the node voltage that is detected.

2. The resistive memory device of claim 1, wherein the write circuit is configured to generate the pulses based on a first voltage, and the voltage detector is configured to receive the first voltage from the write circuit and detect the node voltage based on the first voltage.

3. The resistive memory device of claim 2, wherein the write circuit comprises:

a reference current generator to generate a reference current and output the first voltage; and

a pulse generator to generate the pulses based on the first voltage and provide the pulses via the selected first signal line.

4. The resistive memory device of claim 2, wherein the voltage detector comprises:

a pulse copy unit to generate copy pulses corresponding to the pulses and based on the first voltage; and

a load circuit connected to the pulse copy unit and to receive the plurality of copy pulses.

5. The resistive memory device of claim 4, wherein the voltage detector is configured to detect a voltage level at a connection node between the pulse copy unit and the load circuit as the voltage level of the node voltage.

6. The resistive memory device of claim 4, wherein the pulse copy unit comprises a current mirroring circuit to generate the copy pulses by mirroring the reference current based on the first voltage.

7. The resistive memory device of claim 4, wherein the load circuit comprises a resistor, and the resistor has a resistance value that corresponds to a sum of resistance components of the selected memory cell, and the selected first line and a second signal line connected to the selected memory cell.

8. The resistive memory device of claim 4, wherein the load circuit comprises a reference cell array corresponding to one of a row and a column in the memory cell array.

9. The resistive memory device of claim 8, wherein reference cells of the reference cell array correspond to memory cells, and a voltage that corresponds to a voltage applied to each memory cell corresponding to the reference cell is applied to each of the reference cells.

10. The resistive memory device of claim 1, wherein the pulses comprise a plurality of current pulses, and the write circuit increases at least one of an amplitude and a pulse width of each of the plurality of current pulses according to a number of times programming loops are performed.

11. The resistive memory device of claim 1, wherein the voltage generation circuit is configured to reduce the voltage level of the second inhibit voltage when a voltage level of the node voltage decreases.

12. The resistive memory device of claim 1, wherein the voltage generation circuit is configured to increase the voltage level of the second inhibit voltage when the voltage level of the node voltage increases.

13. A resistive memory device comprising:

a memory cell array comprising a plurality of resistive memory cells arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other;

a write circuit to provide set pulses to a selected first signal line that is connected to a selected memory cell, wherein at least one of an amplitude and a pulse width of each of the set pulses changes based upon a number of times programming loops are performed; and

an inhibit voltage generator to generate a first inhibit voltage and a second inhibit voltage that are respectively applied to unselected first signal lines and unselected second signal lines connected to unselected memory cells, and to change a voltage level of the second inhibit voltage based upon a variation in a voltage of the selected first signal line due to the changes of the set pulses.

14. The resistive memory device of claim 13, wherein the inhibit voltage generator comprises:

a voltage detector to detect a voltage level of the selected first signal line; and

a voltage generation circuit to adjust the voltage level of the second inhibit voltage based upon the detected voltage level of the selected first signal line.

15. The resistive memory device of claim 13, wherein the plurality of set pulses correspond to a plurality of current pulses, and the write circuit comprises a pulse generator to generate the plurality of current pulses based on a reference current;

wherein the inhibit voltage generator comprises a pulse copy unit to generate a plurality of copy current pulses that correspond to the plurality of current pulses based on the reference current, and a load circuit to which the plurality of current pulses are applied; and

wherein the inhibit voltage generator is configured to detect a variation in the voltage level of the selected first signal line based on a voltage at a connection node between the pulse copy unit and the load circuit.

16. A resistive memory device comprising:

a memory cell array comprising a plurality of resistive memory cells arranged at intersections of first and second signal lines;

a write circuit connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and to provide pulses to the selected memory cell; and

a voltage generation circuit to generate a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and to adjust a voltage level of the second inhibit voltage based upon a voltage level of the selected first signal line.

17. The resistive memory device of claim 16, further comprising a voltage detector to detect the voltage level of the selected first signal line;

wherein the voltage generation circuit is configured to adjust the voltage level of the second inhibit voltage based upon the detected voltage level of the selected first signal line.

18. The resistive memory device of claim 16, wherein the pulses comprise a plurality of current pulses, and the write circuit changes at least one of an amplitude and a pulse width of each of the plurality of current pulses based upon a number of times programming loops are performed.

19. The resistive memory device of claim 16, wherein the voltage generation circuit is configured to reduce the voltage level of the second inhibit voltage when the detected voltage level of the selected first signal line decreases.

20. The resistive memory device of claim 16, wherein the voltage generation circuit is configured to increase the voltage level of the second inhibit voltage when the detected voltage level of the selected first signal line increases.