Test partitioning for a non-volatile memory

• US 9,472,285 B2
• Filed: 03/11/2014
• Issued: 10/18/2016
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Byom, Matthew J., Wakrat, Nir J., Herman, Kenneth L.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): BORROMEO, JUANITO C
• Application Number:
  US14/204,162
• Publication Number:
  US 20140192599A1
• Time in Patent Office: 952 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Claims

1. A method of testing non-volatile memory via an interface comprising a flash translation layer and a test region access layer, the method comprising:

creating a removable virtual test partition within a non-volatile memory;

performing a test, using the test region access layer, on the removable virtual test partition, the performing comprising;

erasing a portion of the non-volatile memory contained in the removable virtual partition;

programming a test pattern to a sub-portion of the erased portion;

performing a read operation on the sub-portion; and

determining whether the read operation produces the test pattern;

removing the removable virtual test partition; and

accessing the non-volatile memory using the flash translation layer after the removable virtual test partition has been removed.

2. The method of claim 1, further comprising evaluating results of whether the read operation produces the test pattern.

3. The method of claim 2, further comprising storing results of the test in the non-volatile memory.

4. The method of claim 1, further comprising:

virtually partitioning the non-volatile memory into first and second regions;

storing a test application in the first region of the non-volatile memory; and

executing the test application to run a test in the second region of the non-volatile memory.

5. The method of claim 4, wherein the virtually partitioning comprises:

giving control of physical addresses corresponding to the first region to a first software module; and

giving control of physical addresses corresponding to the second region to a second software module.

6. A method of preparing an electronic device for shipment, the electronic device comprising a non-volatile memory, the method comprising:

creating first and second virtual partitions of the non-volatile memory, wherein first virtual partition is controlled by a first translation layer and the second virtual partition is controlled by a second translation layer;

testing the second virtual partition, the testing further comprising;

erasing a portion of a non-volatile memory;

programming a test pattern to a sub-portion of the erased portion;

performing a read operation on the sub-portion; and

determining whether the read operation produces the test pattern;

storing results of the testing in the first virtual partition; and

removing the virtual partitions before shipment of the electronic device.

7. The method of claim 6, further comprising determining whether the results of the testing meet a predetermined specification, wherein the removing is performed responsive to the determining.

8. The method of claim 6, wherein the creating comprises performing at least one of a firmware update of the electronic device and a software update of the electronic device.

9. The method of claim 6, wherein the testing comprises identifying memory locations in the second virtual partition that contain defects.

10. The method of claim 6, wherein the testing comprises executing a test application stored in the first virtual partition.

11. An electronic device comprising:

a non-volatile memory (NVM);

a NVM interface comprising a NVM translation layer and a test region access layer; and

control circuitry operative to;

create a removable virtual partition;

access the test region access layer to;

erase a portion of a non-volatile memory contained in the removable virtual partition;

program a test pattern to a sub-portion of the erased portion;

perform a read operation on the sub-portion; and

determine whether the read operation produces the test pattern; and

remove the removable virtual partition; and

use the NVM translation layer to access the NVM after the removable virtual partition has been removed.

12. The electronic device of claim 11, wherein the non-volatile memory comprises a flash memory.

13. The electronic device of claim 11, wherein the control circuitry is operative to:

process a test result based on whether the read operation produced the test pattern.

14. The electronic device of claim 12, wherein the control circuitry is operative to:

store the test results in the non-volatile memory.