Power semiconductor switch with plurality of trenches

• US 9,472,403 B2
• Filed: 11/15/2010
• Issued: 10/18/2016
• Est. Priority Date: 03/04/2005
• Status: Active Grant

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Inventors: Carta, Rossano, Bellemo, Laura, Richieri, Giovanni, Merlin, Luigi
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US12/946,787
• Publication Number:
  US 20110278591A1
• Time in Patent Office: 2,164 Days
• Field of Search: 257/134, 257/135, 257/77, 257/E29.265, 257/E29.242
• US Class Current: 1/1
• CPC Class Codes: H01L 21/047 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof.

Claims

1. A power semiconductor device comprising:

a silicon carbide (SiC) semiconductor body of one conductivity formed above a SiC substrate of said one conductivity, said SiC semiconductor body comprising an active region including a plurality of spaced trenches each adjacent a mesa and each trench comprising a region of another conductivity formed into its sidewalls and bottom thereof, each region of said another conductivity being deep enough so that said mesa comprises a first portion of said one conductivity between two opposing regions of said another conductivity;

a contact region of said one conductivity comprising a lower electrical resistivity than said SiC semiconductor body formed above said mesa, said contact region comprises SiC;

a conductive gate electrode formed adjacent to and in contact with said sidewalls and said bottom of each trench, said mesa is free of said conductive gate electrode, said conductive gate electrode directly contacts with said region of another conductivity;

an insulation cap formed above said conductive gate electrode, said insulation cap covers a top surface portion of said contact region, said insulation cap directly contacts with said contact region, said insulation cap has direct contact with a sidewall of said region of another conductivity;

a first power contact in ohmic contact with said contact region; and

a second power contact in ohmic contact with said SiC substrate, said second power contact comprises solderable material,

wherein said power semiconductor device is a junction field effect transistor.

2. The power semiconductor device of claim 1, wherein said SiC semiconductor body comprises epitaxially formed SiC.

3. The power semiconductor device of claim 1, further comprising a termination region, said termination region comprises a plurality of trenches that surround said active region, each of said plurality of trenches of said termination region comprises a conductive electrode.

4. The power semiconductor device of claim 1, wherein said conductive gate electrode comprises a polysilicon of said another conductivity.

5. The power semiconductor device of claim 1, wherein said insulation cap comprises an oxide.

6. The power semiconductor device of claim 1, wherein said insulation cap comprises silicon doxide.

7. The power semiconductor device of claim 1, further comprising a termination region that surrounds said active region.

8. The power semiconductor device of claim 7, wherein said termination region comprises a trench having a region of said another conductivity formed into sidewalls and bottom thereof.

9. The power semiconductor device of claim 1, wherein said first power contact is a source contact.

10. The power semiconductor device of claim 1, wherein said second power contact is a drain contact.

11. The power semiconductor device of claim 1, further comprising a termination region, said termination region comprises a plurality of trenches that surround said active region, each of said plurality of trenches of said termination region comprises a conductive electrode.

16. The power semiconductor device of claim 11, wherein each of said plurality of trenches of said termination region comprises a region of said another conductivity formed into its sidewalls and bottom thereof.

12. A power semiconductor device comprising:

a buffer layer formed above a silicon carbide (SiC) substrate of one conductivity;

a SiC semiconductor body of said one conductivity formed above said buffer layer, said SiC semiconductor body and said SiC substrate have the same conductivity, said SiC semiconductor body comprising an active region including a plurality of spaced trenches each adjacent a mesa and each trench comprising a region of another conductivity formed into its sidewalls and bottom thereof, each region of said another conductivity being deep enough so that said mesa comprises a first portion of said one conductivity between two opposing regions of said another conductivity;

a contact region of said one conductivity comprising a lower electrical resistivity than said SIC semiconductor body formed above said mesa;

a conductive gate electrode formed adjacent to and in contact with said sidewalls and said bottom of each trench, said mesa is free of said conductive gate electrode, said conductive gate electrode directly contacts with said region of another conductivity;

an insulation cap formed above said conductive gate electrode, said insulation cap covers a top surface portion of said contact region, said insulation cap directly contacts with said contact region, said insulation cap has direct contact with a sidewall of said region of another conductivity;

a first power contact in ohmic contact with said contact region; and

a second power contact in ohmic contact with said SiC substrate, said second power contact comprises solderable material,

wherein said power semiconductor device is a junction field effect transistor.

13. The power semiconductor device of claim 12, wherein said buffer layer comprises epitaxially formed SiC.

14. The power semiconductor device of claim 12, wherein said SiC semiconductor body comprises epitaxially formed SiC.

15. The power semiconductor device of claim 12, wherein said contact region comprises epitaxially formed SiC.

17. The power semiconductor device of claim 12, further comprising a termination region that surrounds said active region, said termination region comprises a plurality of trenches, each of said plurality of trenches of said termination region comprises a region of said another conductivity formed into its sidewalls and bottom thereof.

18. The power semiconductor device of claim 12, wherein said insulation cap comprises an oxide.

19. The power semiconductor device of claim 12, wherein said first power contact comprises solderable material.

20. The power semiconductor device of claim 12, further comprising a termination region that surrounds said active region, said termination region comprises a first trench and a second trench, said first trench is wider than said second trench.