Directional chemical oxide etch technique

• US 9,472,415 B2
• Filed: 04/30/2014
• Issued: 10/18/2016
• Est. Priority Date: 04/30/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Alptekin, Emre, Kanakasabapathy, Sivananda K., Ozcan, Ahmet S., Sardesai, Viraj Y., Tran, Cung D.
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US14/265,402
• Publication Number:
  US 20150318184A1
• Time in Patent Office: 902 Days
• Field of Search: 438/424
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench.

Claims

1. A method comprising:

forming a semiconductor structure including a source-drain region in a substrate and adjacent to a gate structure and a nitride layer on the source-drain region, wherein the gate structure includes a gate, a gate cap on a top surface of the gate, and a gate spacer on a sidewall surface of the gate and a sidewall surface of the gate cap;

forming a dielectric layer on the nitride layer and on the gate structure;

forming a contact trench in the dielectric layer by iteratively etching until the nitride layer is exposed, the contact trench exposing the gate cap and the gate spacer, each iterative etching step comprising;

removing a portion of the dielectric layer using an isotropic etching technique, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the contact trench; and

removing the byproduct only from the bottom of the contact trench using an anisotropic etching technique such that the byproduct present along the sidewall of the contract trench remains intact; and

forming a nitride trench in the nitride layer by iteratively etching until the source-drain region is exposed, each iterative etching step comprising;

oxidizing portions of the nitride layer, the gate cap and the gate spacer that are exposed by the contact trench; and

removing the oxidized portions of the nitride layer, the gate cap and the gate spacer using an isotropic etching technique.

2. The method of claim 1, wherein the isotropic etching technique is a chemical oxide removal.

3. The method of claim 1, wherein the anisotropic etching technique is a low bias anisotropic selective sputtering.

4. The method of claim 1, wherein the byproduct is an ammonium hexafluorosilicate.

5. The method of claim 1, wherein gas cluster ion beams are used to oxidize the portions of the nitride layer, the gate cap and the gate spacer.

6. The method of claim 1, wherein low bias oxygen plasma sources are used to oxidize the portions of the nitride layer, the gate cap and the gate spacer.

7. The method of claim 1, wherein chemical oxide removal etching is used to remove the oxidized portions of the nitride layer, the gate cap and the gate spacer.

8. The method of claim 1, wherein the gate cap has a thickness greater than a thickness of the nitride layer.

9. The method of claim 1, wherein each of the nitride layer, the gate cap and the gate spacer comprises a high density plasma nitride.

10. The method of claim 1, wherein the dielectric layer comprises a combination of flowable chemical vapor deposition oxide, high density plasma oxide and plasma enhanced tetra ethyloxy silane oxide.

11. The method of claim 1, further comprising forming a mask layer over the dielectric layer prior to the forming the contact trench.