Multiple bonding layers for thin-wafer handling

• US 9,472,436 B2
• Filed: 05/08/2014
• Issued: 10/18/2016
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Brewer Science Inc.
• Original Assignee: Brewer Science Inc.
• Inventors: Puligadda, Rama, Zhong, Xing-Fu, Flaim, Tony D., McCutcheon, Jeremy
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US14/273,369
• Publication Number:
  US 20140239453A1
• Time in Patent Office: 894 Days
• US Class Current: 1/1
• CPC Class Codes: B32B 38/0008 Electrical discharge treatment, e.g. corona, plasma treatment; wave energy or particle radiation heat treatment B32B38/0036
• CPC Class Codes: B32B 38/10 Removing layers, or parts of layers, mechanically or chemically
• CPC Class Codes: B32B 43/006 Delaminating
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 156/11 Methods of delaminating, per se; i.e. , separating at bonding face
• CPC Class Codes: Y10T 156/1126 Using direct fluid current against work during delaminating
• CPC Class Codes: Y10T 428/24942 : including components having same physical characteristic in differing degree
• CPC Class Codes: Y10T 428/26 : Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
• CPC Class Codes: Y10T 428/31511 : Of epoxy ether
• CPC Class Codes: Y10T 428/31551 : Of polyamidoester [polyurethane, polyisocyanate, polycarbamate, etc.]
• CPC Class Codes: Y10T 428/31663 : As siloxane, silicone or silane
• CPC Class Codes: Y10T 428/31721 : Of polyimide
• CPC Class Codes: Y10T 428/31725 : Of polyamide
• CPC Class Codes: Y10T 428/31935 : Ester, halide or nitrile of addition polymer
• CPC Class Codes: Y10T 428/31938 : Polymer of monoethylenically unsaturated hydrocarbon

Abstract

Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Claims

1. A temporary bonding method comprising:

providing a stack comprising;

a first substrate having a back surface and a device surface, said device surface having a peripheral region and a central region;

a second substrate having a carrier surface;

an edge bond adjacent said peripheral region and said carrier surface; and

at least one layer selected from the group consisting of;

a lift-off layer between said edge bond and said device surface;

a lift-off layer between said edge bond and said carrier surface;

an adhesion promoter layer between said edge bond and said device surface;

an adhesion promoter layer between said edge bond and said carrier surface;

a bonding layer between said edge bond and said device surface; and

a bonding layer between said edge bond and said carrier surface; and

separating said first and second substrates.

2. The method of claim 1, said edge bond being absent from at least some of said central region so as to form a fill zone.

3. The method of claim 2, said stack further comprising a fill layer in said fill zone.

4. The method of claim 3, wherein said stack comprises at least one layer selected from the group consisting of:

a bonding layer between said edge bond and said device surface; and

a bonding layer between said edge bond and said carrier surface.

5. The method of claim 1, wherein said device surface comprises an array of devices selected from the group consisting of integrated circuits;

MEMS;

microsensors;

power semiconductors;

light-emitting diodes;

photonic circuits;

interposers;

embedded passive devices; and

microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, and gallium nitride.

6. The method of claim 1, wherein said second substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics.

7. The method of claim 1, said device surface comprising at least one structure selected from the group consisting of:

solder bumps;

metal posts;

metal pillars; and

structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides.

8. The method of claim 1, wherein said edge bond has a width “

D”

of from about 2 mm to about 15 mm.

9. The method of claim 1, wherein said edge bond is formed is formed from a composition comprising a polymer or oligomer dissolved or dispersed in a solvent system, said polymer or oligomer being selected from the group consisting of polymers and oligomers of cyclic olefins, epoxies, acrylics, silicones, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, cyclic olefins, polyolefin rubbers, and polyurethanes, ethylene-propylene rubbers, polyamide esters, polyimide esters, polyacetals, and polyvinyl butyral.

10. The method of claim 1, further comprising subjecting said stack to processing selected from the group consisting of back-grinding, chemical-mechanical polishing, etching, metal and dielectric deposition, patterning, passivation, annealing, and combinations thereof, prior to separating said first and second substrates.