Integrated circuits having FinFET semiconductor devices and methods of fabricating the same to resist sub-fin current leakage

• US 9,472,554 B2
• Filed: 07/31/2013
• Issued: 10/18/2016
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Hargrove, Michael, Liu, Yanxiang, Gruensfelder, Christian
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US13/955,693
• Publication Number:
  US 20150034941A1
• Time in Patent Office: 1,175 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.

Claims

1. A method of fabricating an integrated circuit having a FinFET, wherein the method comprises:

providing a substrate comprising fins, wherein the fins comprise semiconductor material;

forming a first metal oxide layer over sidewall surfaces of the fins, wherein the first metal oxide layer comprises a first metal oxide;

recessing the first metal oxide layer to a depth below a top surface of the fins to form a recessed first metal oxide layer, wherein the top surface and sidewall surfaces of the fins at a top portion thereof are free from the first metal oxide layer;

depositing a dielectric material different from the first metal oxide over the first metal oxide layer and between the fins to form a dielectric layer, wherein the dielectric layer is recessed below the top surface of the fins to a depth above the recessed first metal oxide layer;

forming a gate electrode structure over the top surface and sidewall surfaces of the fins at the top portion thereof and over the dielectric layer, wherein the recessed first metal oxide layer is recessed beneath the gate electrode structure; and

forming source and drain regions between which a current can flow through a channel under the influence of a bias applied to the gate electrode structure.

2. The method of claim 1, further comprising recessing the first metal oxide layer from the top surface of the fins and from a surface of the substrate between the fins prior to depositing the dielectric material.

3. The method of claim 1, wherein the dielectric material is deposited prior to recessing the first metal oxide layer.

4. The method of claim 3, wherein recessing the first metal oxide layer comprises recessing the first metal oxide layer with an etchant that is selective to the first metal oxide over the dielectric material.

5. The method of claim 1, further comprising forming a second metal oxide layer over the first metal oxide layer prior to recessing the first metal oxide layer, wherein the second metal oxide layer comprises a second metal oxide different from the first metal oxide.

6. The method of claim 5, wherein recessing the first metal oxide layer comprises concurrently recessing the second metal oxide layer and the first metal oxide layer.

7. The method of claim 1, wherein providing the substrate comprising the fins comprises forming the fins in a bulk semiconductor material.

8. The method of claim 1, wherein forming the first metal oxide layer comprises forming the first metal oxide layer through atomic layer deposition.

9. A method of fabricating an integrated circuit having a FinFET, wherein the method comprises:

providing a substrate comprising fins, wherein the fins comprise semiconductor material;

forming a first metal oxide layer over sidewall surfaces of the fins, wherein the first metal oxide layer comprises a first metal oxide;

recessing the first metal oxide layer to a depth below a top surface of the fins to form a recessed first metal oxide layer, wherein the top surface and sidewall surfaces of the fins at a top portion thereof are free from the first metal oxide layer;

forming a gate electrode structure over the top surface and sidewall surfaces of the fins at the top portion thereof, wherein the recessed first metal oxide layer is recessed beneath the gate electrode structure;

forming a second metal oxide layer over the first metal oxide layer prior to recessing the first metal oxide layer, wherein the second metal oxide layer comprises a second metal oxide different from the first metal oxide; and

selectively masking a first fin after forming the first metal oxide layer and prior to forming the second metal oxide layer, wherein the second metal oxide layer is formed on sidewall surfaces of a second fin over the first metal oxide layer on the second fin.

10. The method of claim 9, wherein forming the gate electrode structure comprises forming FinFETs including the gate electrode structure, wherein the FinFETs include an N-type field effect transistor on the second fin and a P-type field effect transistor on the first fin.

11. The method of claim 10, wherein the forming the first metal oxide layer comprises forming the first metal oxide layer comprising hafnium oxide and wherein forming the second metal oxide layer comprises forming the second metal oxide layer comprising aluminum oxide.

12. A method of fabricating an integrated circuit having a FinFET, wherein the method comprises:

providing a substrate comprising fins, wherein the fins comprise semiconductor material;

forming a first metal oxide layer over sidewall surfaces of the fins, wherein the first metal oxide layer comprises a first metal oxide;

selectively masking a first fin after forming the first metal oxide layer, wherein a second fin remains exposed after selectively masking the first fin;

forming a second metal oxide layer over the first metal oxide layer on the second fin, wherein the second metal oxide layer comprises a second metal oxide different from the first metal oxide;

depositing a dielectric material different from the first metal oxide and the second metal oxide over the first metal oxide layer and the second metal oxide layer, where present, to form a dielectric layer;

recessing the first metal oxide layer and the second metal oxide layer, after depositing the dielectric material, with an etchant that is selective to the first metal oxide and the second metal oxide over the dielectric material to a depth below a top surface of the fins to form a recessed first metal oxide layer and a recessed second metal oxide layer, wherein the top surface and sidewall surfaces of the fins at a top portion thereof are free from the first metal oxide layer and the second metal oxide layer;

removing a portion of the dielectric layer to a depth of at least a depth of the recessed first metal oxide layer to form a recessed dielectric layer;

depositing additional dielectric material over the recessed first metal oxide layer and over the recessed dielectric layer to form a reformed dielectric layer;

recessing the reformed dielectric layer to a depth above the recessed first metal oxide layer; and

forming a gate electrode structure over the top surface and sidewall surfaces of the fins at the top portion thereof, wherein the recessed first metal oxide layer and the recessed second metal oxide layer are recessed beneath the gate electrode structure.