CMOS structures with selective tensile strained NFET fins and relaxed PFET fins

• US 9,472,621 B1
• Filed: 12/01/2015
• Issued: 10/18/2016
• Est. Priority Date: 06/29/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Khakifirooz, Ali, Rubin, Joshua M.
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US14/955,738
• Time in Patent Office: 322 Days
• Field of Search: 438/149, 438/175, 438/199, 438/218, 438/424, 438/478, 257/18, 257/55, 257/615, 257/622
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

Claims

1. A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins, the method comprising:

performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate;

selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and

performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

2. The method of claim 1, further comprising forming sidewall spacers on side surfaces of the partially etched tensile strained silicon layer in the PFET region, with the bottom surfaces of the tensile strained silicon layer in the PFET region remaining exposed prior to the oxidizing.

3. The method of claim 2, further comprising:

forming a dielectric spacer layer over the partially etched tensile strained silicon layer;

patterning a block mask to protect the NFET region; and

anisotropically etching horizontal surfaces of the dielectric spacer layer in the PFET region to form the sidewall spacers.

4. The method of claim 3, wherein the dielectric spacer layer comprises a nitride layer.

5. The method of claim 3, wherein the oxidizing comprises furnace heating at a temperature in a range of about 900°

C. to about 1000°

C., and wherein the NFET region is protected from the oxidizing by the dielectric spacer layer.

6. The method of claim 5, further comprising removing the dielectric spacer layer from the NFET region and the sidewall spacers from the PFET region prior to performing the second fin etch.

7. The method of claim 1, wherein the semiconductor substrate comprises a strained silicon on insulator (SSOI) substrate.

8. The method of claim 1, wherein the first fin etch is a timed etch.

9. The method of claim 1, wherein the second fin etch uses an insulator layer below the tensile strained silicon layer as an etch stop.

10. The method of claim 1, wherein the oxidizing comprises a chemical vapor deposition (CVD) of a flowable oxide.

15. The method of claim 1, wherein the first fin etch is a timed etch.

16. The method of claim 1, wherein the second fin etch uses an insulator layer below the tensile strained silicon layer as an etch stop.

17. The method of claim 1, wherein the oxidizing comprises a chemical vapor deposition (CVD) of a flowable oxide.

11. A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins, the method comprising:

forming a hardmask layer on a tensile strained silicon layer of a strained silicon on insulator (SSOI) substrate;

patterning the hardmask layer to define fin patterns;

performing a first, partial fin etch of the tensile strained silicon layer;

forming a dielectric spacer layer over the partially etched tensile strained silicon layer;

patterning a block mask to protect an NFET region of the SSOI substrate;

anisotropically etching horizontal surfaces of the dielectric spacer layer in a PFET region to form sidewall spacers;

oxidizing bottom surfaces of the tensile strained silicon layer in the PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and

performing a second fin etch to define NFET silicon fins in the NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

12. The method of claim 11, wherein the dielectric spacer layer comprises a nitride layer.

13. The method of claim 11, wherein the oxidizing comprises furnace heating at a temperature in a range of about 900°

C. to about 1000°

C., and wherein the NFET region is protected from the oxidizing by the dielectric spacer layer.

14. The method of claim 13, further comprising removing the dielectric spacer layer from the NFET region and the sidewall spacers from the PFET region prior to performing the second fin etch.