Deposit/etch for tapered oxide

• US 9,472,630 B2
• Filed: 02/19/2014
• Issued: 10/18/2016
• Est. Priority Date: 07/25/2012
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Banerjee, Sujit, Grabowski, Wayne B.
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): BARZYKIN, VICTOR V
• Application Number:
  US14/184,554
• Publication Number:
  US 20140187019A1
• Time in Patent Office: 972 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions

Abstract

A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.

Claims

1. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:

etching a trench in the semiconductor wafer;

depositing a first insulating layer with a first thickness in the trench;

etching a first portion of the first insulating layer, wherein the first portion of the first insulating layer is disposed adjacent to the top of the trench;

depositing a second insulating layer with a second thickness in the trench, wherein the second insulating layer overlaps at least a portion of the first insulating layer;

etching a second portion of the second insulating layer, wherein the second portion of the second insulating layer is disposed adjacent to the top of the trench and adjacent to the top of the first insulating layer, and wherein at least some of the second insulating layer remains adjacent to the first insulating layer in the trench after etching the second portion of the second insulating layer;

depositing a third insulating layer with a third thickness in the trench, wherein the third insulating layer overlap at least a portion of the second insulating layer, and wherein the first insulating layer, the second insulating layer, and the third insulating layer are of the same materials; and

etching a third portion of the third insulating layer, wherein the third portion of the third insulating layer is disposed adjacent to the top of the trench, adjacent to the top of the first insulating layer, and adjacent to the top of the second insulating layer, and wherein at least some of the third insulating layer remain adjacent to the second insulating layer in the trench after etching the third portion of the third insulating layer.

2. The method of claim 1, wherein the first and the second and the third thicknesses are approximately the same.

3. The method of claim 1, wherein the first thickness is substantially independent of the slope of the surface that the first insulating layer is being deposited on.

4. The method of claim 1 further comprising:

prior to etching the trench, patterning a hardmask that defines the location of the trench, wherein the patterning the hardmask includes depositing a hardmask material.

5. The method of claim 4, wherein the hardmask material comprises polysilicon.

6. The method of claim 5 further comprising:

prior to patterning the hardmask, depositing a protection layer on the surface of the semiconductor wafer.

7. The method of claim 1, wherein the trench has a sidewall, and wherein the method further comprises:

depositing a conductive material on the first insulating layer and the second insulating layer in the trench, wherein the conductive material is separated from direct contact with the sidewall of the trench by the first insulating layer and the second insulating layer.

8. The method of claim 1, wherein etching the first portion of the first insulating layer and etching the second portion of the second insulating layer are done with an anisotropic etch.