Deposit/etch for tapered oxide
First Claim
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1. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:
- etching a trench in the semiconductor wafer;
depositing a first insulating layer with a first thickness in the trench;
etching a first portion of the first insulating layer, wherein the first portion of the first insulating layer is disposed adjacent to the top of the trench;
depositing a second insulating layer with a second thickness in the trench, wherein the second insulating layer overlaps at least a portion of the first insulating layer;
etching a second portion of the second insulating layer, wherein the second portion of the second insulating layer is disposed adjacent to the top of the trench and adjacent to the top of the first insulating layer, and wherein at least some of the second insulating layer remains adjacent to the first insulating layer in the trench after etching the second portion of the second insulating layer;
depositing a third insulating layer with a third thickness in the trench, wherein the third insulating layer overlap at least a portion of the second insulating layer, and wherein the first insulating layer, the second insulating layer, and the third insulating layer are of the same materials; and
etching a third portion of the third insulating layer, wherein the third portion of the third insulating layer is disposed adjacent to the top of the trench, adjacent to the top of the first insulating layer, and adjacent to the top of the second insulating layer, and wherein at least some of the third insulating layer remain adjacent to the second insulating layer in the trench after etching the third portion of the third insulating layer.
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Abstract
A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
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Citations
8 Claims
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1. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:
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etching a trench in the semiconductor wafer; depositing a first insulating layer with a first thickness in the trench; etching a first portion of the first insulating layer, wherein the first portion of the first insulating layer is disposed adjacent to the top of the trench; depositing a second insulating layer with a second thickness in the trench, wherein the second insulating layer overlaps at least a portion of the first insulating layer; etching a second portion of the second insulating layer, wherein the second portion of the second insulating layer is disposed adjacent to the top of the trench and adjacent to the top of the first insulating layer, and wherein at least some of the second insulating layer remains adjacent to the first insulating layer in the trench after etching the second portion of the second insulating layer; depositing a third insulating layer with a third thickness in the trench, wherein the third insulating layer overlap at least a portion of the second insulating layer, and wherein the first insulating layer, the second insulating layer, and the third insulating layer are of the same materials; and etching a third portion of the third insulating layer, wherein the third portion of the third insulating layer is disposed adjacent to the top of the trench, adjacent to the top of the first insulating layer, and adjacent to the top of the second insulating layer, and wherein at least some of the third insulating layer remain adjacent to the second insulating layer in the trench after etching the third portion of the third insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification