Rail-to-rail input stage circuit with constant transconductance

• US 9,473,122 B1
• Filed: 08/27/2015
• Issued: 10/18/2016
• Est. Priority Date: 08/27/2015
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Shen, Liangguo, Shi, Chunlei, Guan, Hua
• Primary Examiner(s): Le, Dinh T
• Application Number:
  US14/837,364
• Time in Patent Office: 418 Days
• Field of Search: 327306-333, 326 61- 62, 326 80- 81
• US Class Current: 1/1
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03F 2203/45288 Differential amplifier with circuit arrangements to enhance the transconductance
• CPC Class Codes: H03F 2203/45481 the CSC comprising only a direct connection to the supply voltage, no other components being present
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45246 Folded cascode stages
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

Embodiments described herein relate to an improved circuit technique in a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance “gm” throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.

Claims

1. A rail-to-rail input stage circuit comprising:

a first differential pair circuit comprising a first pair of matched transistors having control terminals coupled to a pair of input terminals and a first current source transistor;

a level-shifted differential pair circuit coupled with the first differential pair circuit, the level-shifted differential pair circuit having control terminals coupled to the pair of input terminals; and

a constant transconductance generation circuit coupled with the level-shifted differential pair circuit, the constant transconductance generation circuit comprising;

a first transistor having a control terminal coupled to a control terminal of the first current source transistor in the first differential pair circuit to produce a current through the first transistor corresponding to a current in the first differential pair circuit;

a second transistor configured in series with the first transistor to receive the current in the first transistor and having a control terminal coupled to a voltage based on one or more voltages on the pair of input terminals; and

a current mirror transistor having a first terminal configured to receive a bias current and the current in the first and second transistors, the current mirror transistor configured to mirror a second current to the level-shifted differential pair circuit, wherein the second current is based on a difference between the bias current and the current in the first and second transistors.

2. The rail-to-rail input stage circuit of claim 1 wherein the level-shifted differential pair circuit comprises a source follower circuit and a second differential pair circuit, and wherein the second differential pair circuit comprises a second pair of matched transistors and a second current source transistor, wherein the second current source transistor is coupled to the current mirror transistor to form a current mirror.

3. The rail-to-rail input stage circuit of claim 2 wherein the constant transconductance generation circuit is adapted to adjust current conducting in the second differential pair circuit to maintain the transconductance of the rail-to-rail input stage circuit substantially constant over an entire input common mode voltage range.

4. The rail-to-rail input stage circuit of claim 1 wherein the constant transconductance generation circuit is configured to curtail current conducting in the level-shifted differential pair circuit in response to a current conducting in the first differential pair circuit.

5. The rail-to-rail input stage circuit of claim 4 wherein the constant transconductance generation circuit is configured to turn off the current conducting in the level-shifted differential pair circuit when a common mode voltage on the pair of input terminals is supported by the first differential pair circuit.

6. The rail-to-rail input stage circuit of claim 2 wherein a device size of the second current source transistor in the level-shifted differential circuit is N times greater than a device size of the current mirror transistor in the constant transconductance generation circuit.

7. A method in a rail-to-rail input stage circuit comprising;

receiving an input signal at a first differential pair circuit comprising a first pair of matched transistors having control terminals coupled to a pair of input terminals and a first current source transistor;

shifting up the voltage level of the input signal using a level-shifted differential pair circuit coupled with the first differential pair circuit, the level-shifted differential pair circuit having control terminals coupled to the pair of input terminals;

generating a substantially constant transconductance in the rail-to-rail input stage circuit using a constant transconductance generation circuit, the constant transconductance generation circuit;

generating a current through a first transistor corresponding to a current in the first differential pair circuit, the first transistor having a control terminal coupled to a control terminal of the first current source transistor in the first differential pair circuit;

receiving the current through the first transistor in a second transistor, the second transistor configured in series with the first transistor and having a control terminal coupled to a voltage based on one or more voltages on the pair of input terminals; and

mirroring a second current through a current mirror transistor to the level-shifted differential pair circuit, the current mirror transistor having a first terminal coupled to a bias current and the current in the first and second transistors, wherein the second current is based on a difference between the bias current and the current in the first and second transistors.

8. The method of claim 7 wherein the level-shifted differential pair circuit comprises a source follower circuit and a second differential pair circuit, and wherein the second differential pair circuit comprises a second pair of matched transistors and a second current source transistor, wherein the second current source transistor is coupled to the current mirror transistor to form a current mirror.

9. The method of claim 8 further comprising adjusting current conducting in the second differential pair circuit to maintain the transconductance of the rail-to-rail input stage circuit substantially constant when a common mode voltage on the pair of input terminals is not supported by the first differential pair circuit.

10. The method of claim 7 further comprising curtailing current conducting in the level-shifted differential pair circuit in response to a current conducting in the first differential pair circuit.

11. The method of claim 10 further comprising turning off current conducting in the level-shifted differential pair circuit when a common mode voltage is supported by the first differential pair circuit.

12. The method of claim 8 wherein a device size of the second current source transistor in the level-shifted differential circuit is N times greater than a device size of the current mirror transistor in the constant transconductance generation circuit.

13. A rail-to-rail input stage circuit comprising;

means for receiving an input signal at a first differential pair circuit comprising a first pair of matched transistors having control terminals coupled to a pair of input terminals and a first current source transistor;

means for shifting up the voltage level of the input signal using a level-shifted differential pair circuit coupled with the first differential pair circuit, the level-shifted differential pair circuit having control terminals coupled to the pair of input terminals;

means for generating a substantially constant transconductance in the rail-to-rail input stage circuit using a constant transconductance generation circuit, the constant transconductance generation circuit comprising;

means for generating a first current corresponding to a current in the first differential pair circuit;

means for coupling the first current configured in series with the means for generating the first current, said means for coupling the first current being activated by a voltage based on one or more voltages on the pair of input terminals; and

means for mirroring a second current to the level-shifted differential pair circuit, wherein the second current is based on a difference between a bias current and the first current from the means for coupling the first current.