Integrated circuit device with programmable analog subsystem

• US 9,473,144 B1
• Filed: 03/26/2015
• Issued: 10/18/2016
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Thiagarajan, Eashwar, Kutz, Harold M., Klein, Hans, Johal, Jaskarn Singh, Vanitegem, Jean-Paul, Castor-Perry, Kendall V., Hastings, Mark E., Richardson, Amsby D. Jr., Pai Maroor, Anasuya, Khan, Ata, Seguine, Dennis R., Ozbek, Onur, Liepold, Carl Ferdinand
• Primary Examiner(s): White, Dylan
• Application Number:
  US14/670,295
• Publication Number:
  US 20160329900A1
• Time in Patent Office: 572 Days
• Field of Search: 326 37- 41, 326/47, 340 11- 161, 327564-566
• US Class Current: 1/1
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Claims

1. An integrated circuit (IC) device, comprising:

a plurality of analog blocks, including

at least one fixed function analog circuit, and

a plurality of reconfigurable analog circuit blocks;

at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and

a digital section comprising digital circuits, wherein each analog block includes dedicated signal lines coupled to the at least one analog routing block and at least one of the reconfigurable analog circuit blocks includes at least one direct signal line coupling the at least one of the reconfigurable analog circuit blocks to an external connection of the IC device without passing through any switch, wherein at least one of the analog blocks comprises a programmable reference block (PRB) configured to generate at least four programmable reference values.

2. The IC device of claim 1, wherein:

the PRB has a direct connection for each of its reference values to a plurality of the other analog blocks.

3. The IC device of claim 1, further including:

each of the reconfigurable analog circuits is configurable, at least in part, in response to at least one corresponding digital control signal; and

a digital control section configured to generate the digital control signals.

4. The IC device of claim 3, further including:

a processor circuit; and

the digital control section generates the digital control signals in response to output data from the processor.

5. The IC device of claim 1, wherein:

the plurality of reconfigurable analog circuit blocks includes

at least one continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits, and

at least one discrete time block comprising amplifiers with a reconfigurable switch network having groups of switches commonly controlled by different clock inputs.

6. An integrated circuit (IC) device, comprising:

at least one reconfigurable analog routing signal fabric;

a plurality of analog blocks, including

at least one fixed function analog circuit with dedicated signal lines connected to the analog routing signal fabric,

a plurality of reconfigurable analog circuit blocks with dedicated signal lines connected to the analog routing signal fabric, wherein at least one of the plurality of reconfigurable analog circuit blocks includes at least one direct signal line coupling the at least one of the plurality of reconfigurable analog circuit blocks to an external connection of the IC device without passing through any switch, and wherein at least one of the reconfigurable analog blocks comprises a programmable reference block (PRB) configured to generate at least four programmable reference values; and

a digital section comprising digital circuits.

7. The IC device of claim 6, wherein:

the reconfigurable analog routing signal fabric comprises shielded signal lines.

8. The IC device of claim 7, wherein:

the shielded signal lines include first signal lines formed from one conductive layer, and shielding signals lines formed of the one conductive layer and formed between the first signal lines and electrically coupled to one another.

9. The IC device of claim 8, wherein:

the shielded signal lines further include a shielding conductive layer at a different vertical layer than the one conductive layer, formed over the first signal lines and shielding signal lines and electrically coupled to the shielding signal lines.

10. The IC device of claim 6, wherein:

the fixed function analog circuit includes an analog-to-digital converter (ADC) circuit.

11. The IC device of claim 6, wherein:

the plurality of reconfigurable analog circuit blocks includes

at least one continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits, and

at least one discrete time block comprising amplifiers with a reconfigurable switch network having groups of switches commonly controlled by different clock inputs.

12. A method, comprising:

in response to digital configuration signals, interconnecting a plurality of analog blocks with a reconfigurable analog signal routing fabric, the analog blocks including

at least one fixed function analog circuit with dedicated signal lines connected to the analog signal routing fabric, and

a plurality of reconfigurable analog circuit blocks with dedicated signal lines connected to the analog signal routing fabric, wherein at least one of the plurality of reconfigurable analog circuit blocks includes at least one direct signal line coupling the at least one of the plurality of reconfigurable analog circuit blocks to an external connection of the IC device without passing through any switch, and wherein at least one of the reconfigurable analog blocks comprises a programmable reference block (PRB) configured to generate at least four programmable reference values; and

generating the digital configuration signal with a digital section comprising digital circuits.

13. The method of claim 12, further including:

at least one of the reconfigurable analog circuit blocks is a continuous time block (CTB) comprising a plurality of reconfigurable amplifier circuits; and

executing continuous time signal processing in the at least one CTB block.

14. The method of claim 12, further including:

at least one of the reconfigurable analog circuit blocks comprises a discrete time block having amplifiers with a reconfigurable switch network having groups of switches commonly controlled by different clock inputs; and

executing discrete time signal processing in the discrete time block.

15. The method of claim 12, further including:

generating at least some of the digital configuration signals in response to a processor.

16. The method of claim 12, further including:

generating at least some of the digital configuration signals in response to reconfigurable digital circuits.

17. The method of claim 12, further including:

providing the at least four reference values directly to a plurality of the analog blocks from the programmable reference block.