Apparatus and methods for qualifying HEMT FET devices
First Claim
1. A test method, comprising:
- coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test, and coupling a source terminal of the power transistor device under test to a ground potential;
coupling a current monitor to the drain terminal of the power transistor device under test;
for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal of the power transistor device under test, and for each of the test conditions, applying a voltage pulse to the gate terminal of the power transistor device from the gate pulse generator, the gate pulse rising only after the drain pulse falls below a predetermined threshold for each of the first set of test conditions;
for each of the first set of test conditions, measuring the drain current of the power transistor device under test with the drain current monitor;
for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power transistor device under test, and applying a voltage pulse to the gate terminal of the power transistor device under test as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of the second set of test conditions so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and
for each of the second set of test conditions, measuring the drain current into the power transistor device under test with the drain current monitor.
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Accused Products
Abstract
A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.
8 Citations
20 Claims
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1. A test method, comprising:
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coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test, and coupling a source terminal of the power transistor device under test to a ground potential; coupling a current monitor to the drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal of the power transistor device under test, and for each of the test conditions, applying a voltage pulse to the gate terminal of the power transistor device from the gate pulse generator, the gate pulse rising only after the drain pulse falls below a predetermined threshold for each of the first set of test conditions; for each of the first set of test conditions, measuring the drain current of the power transistor device under test with the drain current monitor; for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power transistor device under test, and applying a voltage pulse to the gate terminal of the power transistor device under test as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of the second set of test conditions so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and for each of the second set of test conditions, measuring the drain current into the power transistor device under test with the drain current monitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for manufacturing power FET devices, comprising:
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providing a semiconductor wafer comprising a plurality of integrated circuits formed thereon, each of the integrated circuits having at least one power FET device comprising a high electron mobility transistor (HEMT) having a gate, a drain and a source terminal; providing a probe card having conductive probes configured to electrically contact the gate, drain and source terminals of the at least one power FET device on one or more of the integrated circuits on the semiconductor wafer, and placing the probe card proximate to and in alignment with the semiconductor wafer; moving at least one of the semiconductor wafer and the probe card to establish electrical contact between ends of the conductive probes and the semiconductor wafer; coupling a gate pulse generator to a probe that is in electrical contact with a gate terminal of the power FET device on the semiconductor wafer, coupling a drain pulse generator to a probe that is in electrical contact with the drain terminal of the power FET device and coupling a ground potential to a probe that is in electrical contact with the source terminal of the power FET device; for a first set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power FET, and for each of the first set of test conditions, activating the gate pulse generator and applying a voltage pulse to the gate terminal of the power FET, the gate pulse rising only after the drain pulse falls to a predetermined low voltage for each test condition so the gate and drain voltage pulses never overlap; for each of the first set of test conditions, measuring the drain current of the power FET device with a drain current monitor; for a second set of test conditions, activating the drain pulse generator and applying a voltage pulse to the drain terminal of the power FET, and activating the gate pulse generator and applying a voltage pulse to the gate terminal of the power FET as the drain pulse falls for each of the second set of test conditions, the drain pulse generator and the gate pulse generator both being active for a portion of each of the second set of test conditions, so that there is some overlap between the voltage pulse applied to the drain terminal and the voltage pulse applied to the gate terminal; and for each of the second set of test conditions, measuring the drain current into the power FET with the drain current monitor. - View Dependent Claims (14, 15, 16, 17, 18)
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19. An apparatus, comprising:
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a first pulse generator configured to generate gate terminal pulses for testing a power FET device under test; a second pulse generator configured to generate drain terminal pulses for testing the power FET device under test; a drain current monitor for measuring the drain current of the power FET device under test; and a controller coupled to the first pulse generator and the second pulse generator for enabling a gate voltage pulse from the first pulse generator and a drain voltage pulse from the second pulse generator; wherein the controller is configured to perform a first set of test conditions corresponding to a soft switching condition where for each test in the first set of test conditions, a drain voltage pulse is output from the second pulse generator, and as the drain pulse falls below a predetermined voltage, a gate voltage pulse is output from the first pulse generator, so that the drain voltage pulse and the gate voltage pulse never overlap, and the controller is further configured to perform a set of second test conditions corresponding to a hard switching condition where, for each test in the second set of test conditions, a drain voltage pulse is output from the second pulse generator, and a gate voltage is output from the first pulse generator as the drain pulse falls, to that for a portion of each test in the second set of test conditions, the gate voltage pulse and the drain voltage pulse overlap. - View Dependent Claims (20)
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Specification