Specification for automatic power management of network-on-chip and system-on-chip

• US 9,477,280 B1
• Filed: 09/24/2014
• Issued: 10/25/2016
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Netspeed Systems, Inc. (Intel Corporation)
• Inventors: Gangwar, Anup, Pusuluri, Vishnu Mohan, Kongetira, Poonacha, Kumar, Sailesh
• Primary Examiner(s): Chen, Xuxing
• Application Number:
  US14/495,689
• Time in Patent Office: 762 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 15/17387 Three dimensional, e.g. hypercubes
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Example implementations described herein are directed to the generation of a specification for automatic power management of a network on chip and/or a system on chip. Such example implementations can include automatically generating a specification comprising at least one of a power domain, an always-on indicator, a voltage domain, a voltage level, and a clock frequency for each of one or more agents of a System on Chip (SoC) and a Network on Chip (NoC), the voltage domain indicative of power supply of the each agent, and the power domain indicative of one or more power switch rules applied to the each agent.

Claims

1. A method, comprising:

automatically generating a specification comprising at least one of a power domain, an always-on indicator, a voltage domain, a voltage level, and a clock frequency for each of one or more agents of a System on Chip (SoC) and a Network on Chip (NoC), the voltage domain indicative of power supply of the each agent, and the power domain indicative of one or more power switch rules applied to the each agent;

wherein the specification further comprises one or more power profiles, each power profile indicative of a mode of operation of the SoC or the SoC use case and wherein each power profile comprises one or more of;

a power and voltage state and a clock frequency of the one or more agents of the SoC and the NoC.

2. The method of claim 1, wherein the one or more power profiles are derived from a traffic profile of the SoC, the traffic profile indicative of which SoC agents are active and intercommunicating in various SoC operating modes.

3. The method of claim 1, wherein the specification further comprises constraints on the one or more of a power state, the voltage level and the clock frequency of the one or more agents of the SoC and the NoC agents when switching between different ones of the one or more power profiles;

the constraints configured for use in automatically determining power sequencing rules for the SoC and the NoC to switch between different power profiles.

4. The method of claim 3, wherein the constraints comprise an order for changing the power state, the voltage level and the clock frequency of the one or more agents of the SoC and the NoC agents.

5. The method of claim 3, wherein the constraints comprise one or more dependencies between the one or more of the power state, voltage level and clock frequency of the one or more agents of the SoC and the NoC.

6. The method of claim 1, wherein the specification further comprises information indicative of a relationship between the one or more of the power domain, the voltage domain, and the clock frequency for the SoC and the NoC.

7. The method of claim 1, wherein the voltage domain comprises a voltage level function.

8. The method of claim 7, wherein the voltage level function is based on an operating one of the one or more power profiles of the SoC and the NoC and operating conditions of the SoC.

9. The method of claim 1, wherein the specification further comprises a topology comprising one or more proximity constraints for a placement of the one or more of the power domains and voltage domains and die area restrictions for the power domain and the voltage domain hardware logic associated with the one or more agents of the SoC and the NoC.

10. The method of claim 1, wherein the specification comprises executable instructions configured to be one of a hierarchical file structure and flat file structure.

11. The method of claim 1, further comprising converting the specification into a format suitable for consumption by an electronic design automation tool.

12. A non-transitory computer readable medium storing instructions for executing a process, the instructions comprising:

automatically generating a specification comprising at least one of a power domain, an always-on indicator, a voltage domain, a voltage level, and a clock frequency for each of one or more agents of a System on Chip (SoC) and a Network on Chip (NoC), the voltage domain indicative of power supply of the each agent, and the power domain indicative of one or more power switch rules applied to the each agent;

wherein the specification further comprises one or more power profiles, each power profile indicative of a mode of operation of the SoC or the SoC use case and wherein each power profile comprises one or more of;

a power and voltage state and a clock frequency of the one or more agents of the SoC and the NoC.

13. The non-transitory computer readable medium of claim 12, wherein the one or more power profiles are derived from a traffic profile of the SoC, the traffic profile indicative of which SoC agents are active and intercommunicating in various SoC operating modes.

14. The non-transitory computer readable medium of claim 12, wherein the specification further comprises constraints on the one or more of a power state, the voltage level and the clock frequency of the one or more agents of the SoC and the NoC agents when switching between different ones of the one or more power profiles;

the constraints configured for use in automatically determining power sequencing rules for the SoC and the NoC to switch between different power profiles.

15. The non-transitory computer readable medium of claim 14, wherein the constraints comprise an order for changing the power state, the voltage level and the clock frequency of the one or more agents of the SoC and the NoC agents.

16. The non-transitory computer readable medium of claim 14, wherein the constraints comprise one or more dependencies between the one or more of the power state, voltage level and clock frequency of the one or more agents of the SoC and the NoC.

17. The non-transitory computer readable medium of claim 12, wherein the specification further comprises information indicative of a relationship between the one or more of the power domain, the voltage domain, i and the clock frequency for the SoC and the NoC.

18. The non-transitory computer readable medium of claim 12, wherein the voltage domain comprises a voltage level function.

19. A method, comprising:

processing an input specification comprising a Network on Chip (NoC) design, a System on Chip (SoC) design, one or more power switching sequences for hardware elements of the NoC design and hardware elements of the SoC design, and one or more power profiles to generate a power management design for the SoC design and the NoC design.

20. The method of claim 19, wherein the input specification further comprises isolation cell information for hardware elements of the NoC design.