Memory access requests in hybrid memory system
First Claim
1. A device, comprising:
- a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured toreceive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs, the memory access requests comprising;
read requests, each read request respectively including a host LBA range;
promotion requests, each promotion request respectively including a host LBA range that is aligned to secondary memory LBA clusters; and
invalidate requests, each invalidate request respectively including a host LBA range that is aligned to secondary memory LBA clusters;
route the incoming memory access requests to a set of incoming queues, the set of incoming queues comprising an incoming free queue containing a number of incoming nodes;
map the range of host LBAs into clusters of secondary memory LBAs;
transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory LBAs;
route the outgoing memory access requests from the incoming queues into a set of outgoing queues, the set of outgoing queues comprising a set of outgoing execute queues and an outgoing free queue that includes a number of outgoing nodes;
use an outgoing node to store data about the outgoing memory access request;
make the outgoing node that stores the data about the outgoing memory access request unavailable to store data about other outgoing memory access requests;
return the outgoing node to the outgoing free queue after at least a portion of the outgoing memory access request has been executed; and
access the secondary memory using the outgoing memory access requests.
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Accused Products
Abstract
Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is mapped to clusters of secondary memory LBAs, the secondary memory LBAs corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory LBAs or one or more clusters of secondary memory LBAs. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests.
75 Citations
15 Claims
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1. A device, comprising:
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a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the primary memory including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to receive incoming memory access requests from the host processor, the memory access requests including a range of host LBAs, the memory access requests comprising; read requests, each read request respectively including a host LBA range; promotion requests, each promotion request respectively including a host LBA range that is aligned to secondary memory LBA clusters; and invalidate requests, each invalidate request respectively including a host LBA range that is aligned to secondary memory LBA clusters; route the incoming memory access requests to a set of incoming queues, the set of incoming queues comprising an incoming free queue containing a number of incoming nodes; map the range of host LBAs into clusters of secondary memory LBAs; transform each incoming memory access request into one or more outgoing memory access requests, each outgoing memory access request including a range or cluster of secondary memory LBAs; route the outgoing memory access requests from the incoming queues into a set of outgoing queues, the set of outgoing queues comprising a set of outgoing execute queues and an outgoing free queue that includes a number of outgoing nodes; use an outgoing node to store data about the outgoing memory access request; make the outgoing node that stores the data about the outgoing memory access request unavailable to store data about other outgoing memory access requests; return the outgoing node to the outgoing free queue after at least a portion of the outgoing memory access request has been executed; and access the secondary memory using the outgoing memory access requests. - View Dependent Claims (2, 3, 4)
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5. A method of operating a hybrid memory system that includes a primary memory and a secondary memory, the method comprising:
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routing incoming memory access requests in a set of incoming queues, the set of incoming queues comprising; an incoming free queue containing a number of incoming nodes; a receive queue configured to queue each of the incoming memory access requests; a set of ready queues, each ready queue of the set of ready queues configured to queue memory access requests that are waiting for execution, the set of ready queues comprising; a read ready queue configured to queue read requests; a promotion ready queue configured to queue promotion requests; and an invalidate ready queue configured to queue invalidate requests; an execute queue configured to queue data access requests that are being executed; and an overlap queue configured to queue each memory access request having a host LBA range that overlaps with a host LBA range of a memory access request in the set of ready queues or the execute queue, the incoming memory access requests comprising a range of host logical block addresses (LBAs) that correspond to a memory space of the primary memory, the memory access requests comprising; read requests, each read request respectively including a host LBA range; promotion requests, each promotion request respectively including a host LBA range that is aligned to secondary memory LBA clusters; and invalidate requests, each invalidate request respectively including a host LBA range that is aligned to secondary memory LBA clusters; mapping the host LBA range to clusters of secondary memory LBAs, the secondary memory LBAs corresponding to a memory space of the secondary memory; transforming each incoming memory access request queued in the set of incoming queues into one or more outgoing memory access requests, the outgoing memory comprising a range of secondary memory LBAs or one or more clusters of secondary memory LBAs; routing the one or more outgoing memory access requests in a set of outgoing queues; and accessing the secondary memory using the outgoing memory access requests. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. A controller system for a hybrid memory system, the controller comprising:
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a hybrid controller configured to manage data transfers between a host processor and a flash memory, the flash memory configured to serve as a cache for a magnetic disk, the magnetic disk including a memory space corresponding to host logical block addresses (LBAs), the hybrid controller configured to the hybrid controller configured to; receive the incoming memory access requests from a higher layer of the hybrid controller, the memory access requests comprising; read requests, each read request respectively including a host LBA range; promotion requests, each promotion request respectively including a host LBA range that is aligned to flash memory LBA clusters; and invalidate requests, each invalidate request respectively including a host LBA range that is aligned to flash memory LBA clusters; route the incoming data access requests in a set of incoming queue comprising; generating an error message if there are no free nodes in the incoming free queue; routing an incoming memory access request to the receive queue if there is an available node in the incoming free queue; using an incoming node to store data about the incoming memory access request; making the incoming node that stores the data about the incoming memory access request unavailable to store data about other incoming memory access requests; and returning the incoming node to the incoming free queue after at least a portion of the incoming memory access request has been executed; transform each of the memory access requests from the set of incoming queues into a plurality of outgoing memory access requests; route the plurality of outgoing memory access requests in a set of outgoing queues; and send the outgoing memory access requests to a lower layer of the hybrid controller. - View Dependent Claims (14, 15)
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Specification